X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/hpcc2014.git/blobdiff_plain/28e01316fd4048f6765d2771d36cd4565cba5421..d0df474d3df1a66a6e43d1513fc3e9ed1248d2ed:/hpcc.tex?ds=sidebyside diff --git a/hpcc.tex b/hpcc.tex index 04c5403..22fa047 100644 --- a/hpcc.tex +++ b/hpcc.tex @@ -1,4 +1,3 @@ - \documentclass[conference]{IEEEtran} \usepackage[T1]{fontenc} @@ -509,7 +508,7 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} = \begin{table}[!t] \centering \caption{Relative gain of the multisplitting algorithm compared to GMRES for - different configurations with 2 clusters, each one composed of 50 nodes.} + different configurations with 2 clusters, each one composed of 50 nodes. Latency = $20$ms} \label{tab.cluster.2x50} \begin{mytable}{5} @@ -517,14 +516,14 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} = bandwidth (Mbit/s) & 5 & 5 & 5 & 5 & 5 \\ \hline - latency (ms) - & 20 & 20 & 20 & 20 & 20 \\ - \hline + % latency (ms) + % & 20 & 20 & 20 & 20 & 20 \\ + %\hline power (GFlops) & 1 & 1 & 1 & 1.5 & 1.5 \\ \hline size $(N)$ - & 62 & 62 & 62 & 100 & 100 \\ + & $62^3$ & $62^3$ & $62^3$ & $100^3$ & $100^3$ \\ \hline Precision & \np{E-5} & \np{E-8} & \np{E-9} & \np{E-11} & \np{E-11} \\ @@ -542,14 +541,14 @@ $\text{62}^\text{3} = \text{\np{238328}}$ to $\text{150}^\text{3} = bandwidth (Mbit/s) & 50 & 50 & 50 & 50 & 50 \\ % & 10 & 10 \\ \hline - latency (ms) - & 20 & 20 & 20 & 20 & 20 \\ % & 0.03 & 0.01 \\ - \hline + %latency (ms) + %& 20 & 20 & 20 & 20 & 20 \\ % & 0.03 & 0.01 \\ + %\hline Power (GFlops) & 1.5 & 1.5 & 1.5 & 1.5 & 1.5 \\ % & 1 & 1.5 \\ \hline size $(N)$ - & 110 & 120 & 130 & 140 & 150 \\ % & 171 & 171 \\ + & $110^3$ & $120^3$ & $130^3$ & $140^3$ & $150^3$ \\ % & 171 & 171 \\ \hline Precision & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} & \np{E-11} \\ % & \np{E-5} & \np{E-5} \\ @@ -715,7 +714,7 @@ tool to run efficiently an iterative parallel algorithm in asynchronous mode in a grid architecture. In future works, we plan to extend our experimentations to larger scale platforms by increasing the number of computing cores and the number of clusters. -We will also have to increase the size of the input problem which will require the use of a more powerful simulation platform. At last, we expect to compare our simulation results to real execution results on real architectures in order to experimentally validate our study. +We will also have to increase the size of the input problem which will require the use of a more powerful simulation platform. At last, we expect to compare our simulation results to real execution results on real architectures in order to better experimentally validate our study. Finally, we also plan to study other problems with the multisplitting method and other asynchronous iterative methods. \section*{Acknowledgment}