+ The main problem of the simultaneous methods is that the necessary\r
+time needed for the convergence is increased with the increasing\r
+of the degree of the polynomial. The parallelization of these\r
+algorithms will improve the convergence time. Researchers usually\r
+adopt one of the two following approaches to parallelize root\r
+finding algorithms. One approach is to reduce the total number of\r
+iterations as implemented by Miranker\r
+~\cite{Mirankar68,Mirankar71}, Schedler~\cite{Schedler72} and\r
+Winogard~\cite{Winogard72}. Another approach is to reduce the\r
+computation time per iteration, as reported\r
+in~\cite{Benall68,Jana06,Janall99,Riceall06}. There are many\r
+schemes for simultaneous approximations of all roots of a given\r
+polynomial. Several works on different methods and issues of root\r
+finding have been reported in~\cite{Azad07,Gemignani07,Kalantari08\r
+,Skachek08,Zhancall08,Zhuall08}. However, Durand-Kerner and\r
+Ehrlich methods are the most practical choices among\r
+them~\cite{Bini04}. These two methods have been extensively\r
+studied for parallelization due to their following advantages. The\r
+computation involved in these methods has some inherent\r
+parallelism that can be suitably exploited by SIMD machines.\r
+Moreover, they have fast rate of convergence (quadratic for the\r
+Durand-Kerner method and cubic for the Ehrlich). Various parallel\r
+algorithms reported for these methods can be found\r
+in~\cite{Cosnard90, Freeman89,Freemanall90,,Jana99,Janall99}.\r
+Freeman and Bane~\cite{Freemanall90} presented two parallel\r
+algorithms on a local memory MIMD computer with the compute-to\r
+communication time ratio O(n). However, their algorithms require\r
+each processor to communicate its current approximation to all\r
+other processors at the end of each iteration. Therefore they\r
+cause a high degree of memory conflict. Recently the author\r
+in~\cite{Mirankar71} proposed two versions of parallel algorithm\r
+for the Durand-Kerner method, and Aberth method on an on model of\r
+Optoelectronic Transpose Interconnection System (OTIS).The\r
+algorithms are mapped on an OTIS-2D torus using N processors. This\r
+solution need N processors to compute N roots, that it is not\r
+practical (is not suitable to compute large polynomial's degrees).\r
+Until then, the related works are not able to compute the root of\r
+the large polynomial's degrees (higher then 1000) and with small\r
+time.\r
+\r
+ Finding polynomial roots rapidly and accurately it is our\r
+objective, with the apparition of the CUDA(Compute Unified Device\r
+Architecture), finding the roots of polynomials becomes rewarding\r
+and very interesting, CUDA adopts a totally new computing\r
+architecture to use the hardware resources provided by GPU in\r
+order to offer a stronger computing ability to the massive data\r
+computing.in~\cite{Kahinall14} we proposed the first implantation\r
+of the root finding polynomials method on GPU (Graphics Processing\r
+Unit),which is the Durand-Kerner method. The main result prove\r
+that a parallel implementation is 10 times as fast as the\r
+sequential implementation on a single CPU for high degree\r
+polynomials that is greater than about 48000. Indeed, in this\r
+paper we present a parallel implementation of Aberth's method on\r
+GPU, more details are discussed in the following of this paper.\r
+\r
+\section {A parallel implementation of Aberth's method}\r
+\subsection{Background on the GPU architecture}\r
+A GPU is viewed as an accelerator for the data-parallel and\r
+intensive arithmetic computations. It draws its computing power\r
+from the parallel nature of its hardware and software\r
+architectures. A GPU is composed of hundreds of Streaming\r
+Processors (SPs) organized in several blocks called Streaming\r
+Multiprocessors (SMs). It also has a memory hierarchy. It has a\r
+private read-write local memory per SP, fast shared memory and\r
+read-only constant and texture caches per SM and a read-write\r
+global memory shared by all its SPs~\cite{NVIDIA10}\r
+\r
+ On a CPU equipped with a GPU, all the data-parallel and intensive\r
+functions of an application running on the CPU are off-loaded onto\r
+the GPU in order to accelerate their computations. A similar\r
+data-parallel function is executed on a GPU as a kernel by\r
+thousands or even millions of parallel threads, grouped together\r
+as a grid of thread blocks. Therefore, each SM of the GPU executes\r
+one or more thread blocks in SIMD fashion (Single Instruction,\r
+Multiple Data) and in turn each SP of a GPU SM runs one or more\r
+threads within a block in SIMT fashion (Single Instruction,\r
+Multiple threads). Indeed at any given clock cycle, the threads\r
+execute the same instruction of a kernel, but each of them\r
+operates on different data.\r
+ GPUs only work on data filled in their\r
+global memories and the final results of their kernel executions\r
+must be communicated to their CPUs. Hence, the data must be\r
+transferred in and out of the GPU. However, the speed of memory\r
+copy between the GPU and the CPU is slower than the memory\r
+bandwidths of the GPU memories and, thus, it dramatically affects\r
+the performances of GPU computations. Accordingly, it is necessary\r
+to limit data transfers between the GPU and its CPU during the\r
+computations.\r
+\subsection{Background on the CUDA Programming Model}\r
+\r
+The CUDA programming model is similar in style to a single program\r
+multiple-data (SPMD) softwaremodel. The GPU is treated as a\r
+coprocessor that executes data-parallel kernel functions. CUDA\r
+provides three key abstractions, a hierarchy of thread groups,\r
+shared memories, and barrier synchronization. Threads have a three\r
+level hierarchy. A grid is a set of thread blocks that execute a\r
+kernel function. Each grid consists of blocks of threads. Each\r
+block is composed of hundreds of threads. Threads within one block\r
+can share data using shared memory and can be synchronized at a\r
+barrier. All threads within a block are executed concurrently on a\r
+multithreaded architecture.The programmer specifies the number of\r
+threads per block, and the number of blocks per grid. A thread in\r
+the CUDA programming language is much lighter weight than a thread\r
+in traditional operating systems. A thread in CUDA typically\r
+processes one data element at a time. The CUDA programming model\r
+has two shared read-write memory spaces, the shared memory space\r
+and the global memory space. The shared memory is local to a block\r
+and the global memory space is accessible by all blocks. CUDA also\r
+provides two read-only memory spaces, the constant space and the\r
+texture space, which reside in external DRAM, and are accessed via\r
+read-only caches\r
+\r
+\subsection{A parallel implementation of the Aberth's method }\r
+%%\subsection{A CUDA implementation of the Aberth's method }\r
+%%\subsection{A GPU implementation of the Aberth's method }\r
+\r
+\r
+\r
+\subsubsection{A sequential Aberth algorithm}\r
+The means steps of Aberth's method can expressed as an algorithm\r
+like:\r
+ \r
+\begin{algorithm}[H]\r
+\LinesNumbered\r
+\caption{Algorithm to find root polynomial with Aberth method}\r
+\r
+\KwIn{$Z^{0}$(Initial root's vector),$\varepsilon$ (error\r
+tolerance threshold),P(Polynomial to solve)}\r
+\r
+\KwOut {Z(The solution root's vector)}\r
+\r
+\BlankLine\r
+\r
+Initialization of the parameter of the polynomial to solve\;\r
+Initialization of the solution vector $Z^{0}$\;\r
+\r
+\While {$\Delta z_{max}\succ \epsilon$}{\r
+ Let $\Delta z_{max}=0$\;\r
+\For{$j \gets 0 $ \KwTo $n$}{\r
+$ZPrec\left[j\right]=Z\left[j\right]$\;\r
+$Z\left[j\right]=H\left(j,Z\right)$\;\r
+}\r
+\r
+\For{$i \gets 0 $ \KwTo $n-1$}{\r
+$c=\frac{\left|Z\left[i\right]-ZPrec\left[i\right]\right|}{Z\left[i\right]}$\;\r
+\If{$c\succ\Delta z_{max}$ }{\r
+$\Delta z_{max}$=c\;}\r
+}\r
+}\r
+\end{algorithm}\r
+~\\ \r
+~\\ \r
+In this sequential algorithm one thread CPU execute all steps, let see the step 3 the execution of the iterative function , 2 instructions are needed, the first instruction \textit{save} the solution vector for the previous iteration, the second instruction \textit{update} or compute a new values of the roots.\r
+We have two manner to execute the iterative function, taking a Jacobi iteration who need all the previous value $z^{(k)}_{i}$ to compute the new value $z^{(k+1)}_{i}$we have:\r
+\r
+\begin{equation}\r
+H(i,z^{k+1})=\frac{p(z^{(k)}_{i})}{p'(z^{(k)}_{i})-p(z^{(k)}_{i})\sum^{n}_{j=1 j\neq i}\frac{1}{z^{(k)}_{i}-z^{(k)}_{j}}}, i=1,...,n.\r
+\end{equation}\r
+\r
+Or with the Gauss-seidel iteration, we have:\r
+\begin{equation}\r
+H(i,z^{k+1})=\frac{p(z^{(k)}_{i})}{p'(z^{(k)}_{i})-p(z^{(k)}_{i})\sum^{i-1}_{j=1}\frac{1}{z^{(k)}_{i}-z^{(k)}_{j}}+\sum^{n}_{j=i+1}\frac{1}{z^{(k)}_{i}-z^{(k)}_{j}}}, i=1,...,n.\r
+\end{equation}\r
+\r
+In formula(16) the iteration function use the $z^{k+1}_{i}$ computed in the current iteration to compute the rest of the roots, which take him to converge more quickly compare to the jacobi iteration (it's well now that the Gauss-seidel iteration converge more quickly because they used the most fresh computed root, so we used Gauss-seidel iteration.)\r
+\r
+The steps 4 of the Aberth's method compute the convergence of the roots, using(9) formula.\r
+Both steps 3 and 4 use 1 thread to compute N roots on CPU, which is faster and hard, it make the algorithm faster and hard for the large polynomial's roots finding.\r
+\r
+\paragraph{The execution time}\r
+Let $T_{i}(N)$: the time to compute one new root's value of the step 3,$T_{i}$ depend on the polynomial's degrees N, when N increase $T_{i}$ increase to.We need $N.T_{i}(N)$ to compute all the new root's value in one iteration on the step 3.\r
+\r
+Let $T_{j}$: the time to compute one root's convergence value of the step 4, we need $N.T_{j}$ to compute all the root's convergence value in one iteration on the step 4.\r
+\r
+The execution time for both steps 3 and 4 can see like:\r
+\begin{equation}\r
+T_{exe}=N(T_{i}(N)+T_{j})+O(n).\r
+\end{equation}\r
+Let Nbr\_iter the number of iteration necessary to compute all the roots,so the total execution time $Total\_time_{exe}$ can give like:\r
+\r
+\begin{equation}\r
+Total\_time_{exe}=\left[N\left(T_{i}(N)+T_{j}\right)+O(n)\right].Nbr\_iter.\r
+\end{equation}\r
+The execution time increase with the increasing of the polynomial's root, which take necessary to parallilize this step to reduce the execution time. In the following paper you explain how we parrallelize this step using GPU architecture with CUDA platform.\r
+\r
+\subsubsection{Parralelize the steps on GPU }\r
+On the CPU Aberth algorithm both steps 3 and 4 contain the loop \verb=for= , it use one thread to execute all the instruction in the loop N times.Here we explain how the GPU architecture can compute this loop and reduce the execution time.\r
+The GPU architecture affect the execution of this loop to a groups of parallel threads organized as a grid of blocks each block contain a number of threads. All threads within a block are executed concurrently in parallel. the instruction are executed as a kernel.\r
+\r
+Let nbr\_thread be the number of threads executed in parallel, so you can easily transform the (18)formula like this: \r
+\r
+\begin{equation}\r
+Total\_time_{exe}=\left[\frac{N}{nbr\_thread}\left(T_{i}(N)+T_{j}\right)+O(n)\right].Nbr\_iter.\r
+\end{equation}\r
+\r
+In theory, the $Total\_time_{exe}$ on GPU is speed up nbr\_thread times as a $Total\_time_{exe}$ on CPU. We show more details in the experiment part. \r
+~\\\r
+~\\\r
+In CUDA platform, All the instruction of the loop \verb=for= are executed by the GPU as a kernel form. A kernel is a procedure written in CUDA and defined by a heading \verb=__global__=, which means that it is to be executed by the GPU.the following algorithm see the kernels created for the step 3 and 4 of the Aberth algorithm:\r
+\r
+\begin{algorithm}[H]\r
+\LinesNumbered\r
+\caption{Algorithm to find root polynomial with Aberth method}\r
+\r
+\KwIn{$Z^{0}$(Initial root's vector),$\varepsilon$ (error\r
+tolerance threshold),P(Polynomial to solve)}\r
+\r
+\KwOut {Z(The solution root's vector)}\r
+\r
+\BlankLine\r
+\r
+Initialization of the parameter of the polynomial to solve\;\r
+Initialization of the solution vector $Z^{0}$\;\r
+\r
+\While {$\Delta z_{max}\succ \epsilon$}{\r
+ Let $\Delta z_{max}=0$\;\r
+$\prec DimGrid,DimBloc\succ kernel\_save(d\_Z^{k-1});$\r
+$\prec DimGrid,DimBloc \succ kernel\_update(d\_z^{k});$\r
+\r
+$\prec DimGrid,DimBloc\succ kernel\_testConverge (d_?z_{max},d_Z^{k},d_Z^{k-1});$\r
+}\r
+\end{algorithm}\r
+~\\ \r
+\r