-\subsection{CUDA}%L'article en anglais Multi-GPU and multi-CPU accelerated FDTD scheme for vibroacoustic applications
- CUDA (an acronym for Compute Unified Device Architecture) is a parallel computing architecture developed by NVIDIA [28]. The
-unit of execution in CUDA is called a thread. Each thread executes the kernel by the streaming processors in parallel. In CUDA,
-a group of threads that are executed together is called thread blocks, and the computational grid consists of a grid of thread
-blocks. Additionally, a thread block can use the shared memory on a single multiprocessor as while as the grid executes a single
-CUDA program logically in parallel. Thus in CUDA programming, it is necessary to design carefully the arrangement of the thread
-blocks in order to ensure low latency and a proper usage of shared memory, since it can be shared only in a thread block
-scope. The effective bandwidth of each memory space depends on the memory access pattern. Since the global memory has lower
-bandwidth than the shared memory, the global memory accesses should be minimized.
+\subsection{CUDA}
+%CUDA (is an acronym of the Compute Unified Device Architecture) is a parallel computing architecture developed by NVIDIA~\cite{CUDA10}.The unit of execution in CUDA is called a thread. Each thread executes a kernel by the streaming processors in parallel. In CUDA, a group of threads that are executed together is called a thread block, and the computational grid consists of a grid of thread blocks. Additionally, a thread block can use the shared memory on a single multiprocessor while the grid executes a single CUDA program logically in parallel. Thus in CUDA programming, it is necessary to design carefully the arrangement of the thread blocks in order to ensure low latency and a proper usage of shared memory, since it can be shared only in a thread block scope. The effective bandwidth of each memory space depends on the memory access pattern. Since the global memory has lower bandwidth than the shared memory, the global memory accesses should be minimized.
+
+CUDA (Compute Unified Device Architecture) is a parallel computing architecture developed by NVIDIA~\cite{CUDA15} for GPUs. It provides a high level GPGPU-based programming model to program GPUs for general purpose computations and non-graphic applications. The GPU is viewed as an accelerator such that data-parallel operations of a CUDA program running on a CPU are off-loaded onto GPU and executed by this later. The data-parallel operations executed by GPUs are called kernels. The same kernel is executed in parallel by a large number of threads organized in grids of thread blocks, such that each GPU multiprocessor executes one or more thread blocks in SIMD fashion (Single Instruction, Multiple Data) and in turn each core of the multiprocessor executes one or more threads within a block. Threads within a block can cooperate by sharing data through a fast shared memory and coordinate their execution through synchronization points. In contrast, within a grid of thread blocks, there is no synchronization at all between blocks. The GPU only works on data filled in the global memory and the final results of the kernel executions must be transferred out of the GPU. In the GPU, the global memory has lower bandwidth than the shared memory associated to each multiprocessor. Thus in the CUDA programming, it is necessary to design carefully the arrangement of the thread blocks in order to ensure low latency and a proper usage of the shared memory, and the global memory accesses should be minimized.
+
+%We introduced three paradigms of parallel programming. Our objective consists in implementing a root finding polynomial algorithm on multiple GPUs. To this end, it is primordial to know how to manage CUDA contexts of different GPUs. A direct method for controlling the various GPUs is to use as many threads or processes as GPU devices. We can choose the GPU index based on the identifier of OpenMP thread or the rank of the MPI process. Both approaches will be investigated.
+
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+
+\section{The Ehrlich-Aberth algorithm on a GPU}
+\label{sec3}
+
+\subsection{The EA method}
+%A cubically convergent iteration method to find zeros of
+%polynomials was proposed by O. Aberth~\cite{Aberth73}. The
+%Ehrlich-Aberth (EA is short) method contains 4 main steps, presented in what
+%follows.
+
+%The Aberth method is a purely algebraic derivation.
+%To illustrate the derivation, we let $w_{i}(z)$ be the product of linear factors
+
+%\begin{equation}
+%w_{i}(z)=\prod_{j=1,j \neq i}^{n} (z-x_{j})
+%\end{equation}
+
+%And let a rational function $R_{i}(z)$ be the correction term of the
+%Weistrass method~\cite{Weierstrass03}
+
+%\begin{equation}
+%R_{i}(z)=\frac{p(z)}{w_{i}(z)} , i=1,2,...,n.
+%\end{equation}
+
+%Differentiating the rational function $R_{i}(z)$ and applying the
+%Newton method, we have:
+
+%\begin{equation}
+%\frac{R_{i}(z)}{R_{i}^{'}(z)}= \frac{p(z)}{p^{'}(z)-p(z)\frac{w_{i}(z)}{w_{i}^{'}(z)}}= \frac{p(z)}{p^{'}(z)-p(z) \sum _{j=1,j \neq i}^{n}\frac{1}{z-x_{j}}}, i=1,2,...,n
+%\end{equation}
+%where R_{i}^{'}(z)is the rational function derivative of F evaluated in the point z
+%Substituting $x_{j}$ for $z_{j}$ we obtain the Aberth iteration method.%
+
+
+%\subsubsection{Polynomials Initialization}
+%The initialization of a polynomial $p(z)$ is done by setting each of the $n$ complex coefficients %$a_{i}$:
