X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/mpi-energy2.git/blobdiff_plain/26cbe1ae1953d2db886af547cac5067e697ac555..208a7faf6fcd36c659b1ae7043b67ccc39ea2a9c:/mpi-energy2-extension/my_reference.bib?ds=inline

diff --git a/mpi-energy2-extension/my_reference.bib b/mpi-energy2-extension/my_reference.bib
index 81d1c9f..2c7e80f 100644
--- a/mpi-energy2-extension/my_reference.bib
+++ b/mpi-energy2-extension/my_reference.bib
@@ -798,6 +798,10 @@ ISSN={1045-9219},}
   url =          {http://www.eia.gov/}
 }
 
+@MISC{U.S_Annual.Energy.Outlook.2015,
+  title =        {{U.S. Energy Information Administration, Annual Energy Outlook 2015}},
+  url =          {http://www.eia.gov/}
+}
 @inproceedings{pdsec2015,
   title = {Energy Consumption Reduction with DVFS for Message Passing Iterative Applications on Heterogeneous Architectures},
   author = {Charr, Jean-Claude and Couturier, Rapha\~{A}«l and Fanfakh, Ahmed and Giersch, Arnaud},
@@ -834,3 +838,50 @@ pages={1451-1476}
   year={2013},
   publisher={Springer Science \& Business Media}
 }
+
+@article{EDP_for_multi_processors,
+year={2015},
+journal={Human-centric Computing and Information Sciences},
+eid={28},
+volume={5},
+number={1},
+doi={10.1186/s13673-015-0046-x},
+title={An energy-delay product study on chip multi-processors for variable stage pipelining},
+url={http://dx.doi.org/10.1186/s13673-015-0046-x},
+publisher={Springer Berlin Heidelberg},
+keywords={Chip multi-processors (CMP); Variable stage pipelining (VSP); Power-performance; Optimal pipeline},
+author={Saravanan, Vijayalakshmi and Anpalagan, Alagan and Woungang, Isaac}
+}
+
+
+@INPROCEEDINGS{Energy_aware_application_scheduling,
+author={Jian Chen and John, L.K.},
+booktitle={Workload Characterization, 2008. IISWC 2008. IEEE International Symposium on},
+title={Energy-aware application scheduling on a heterogeneous multi-core system},
+year={2008},
+pages={5-13},
+keywords={fuzzy logic;power aware computing;processor scheduling;resource allocation;branch transition rate;energy-aware application scheduling mechanism;fuzzy logic;heterogeneous multicore processor;instruction dependency distance;power efficient computing;program execution;random scheduling approach;resource requirement;suitability-guided program scheduling mechanism;workload balancing;Algorithm design and analysis;Application software;Energy consumption;Fuzzy logic;Hardware;Multicore processing;Power engineering and energy;Power engineering computing;Processor scheduling;Scheduling algorithm},
+doi={10.1109/IISWC.2008.4636086},
+month={Sept}
+}
+
+@INPROCEEDINGS{elusive_metric_for_low_power,
+    author = {Hsien-hsin S. Lee and Joshua B. Fryman and A. Utku Diril and Yuvraj S. Dhillon},
+    title = {The elusive metric for low-power architecture research},
+    booktitle = {In Proceedings of the Workshop on Complexity-Effective Design},
+    year = {2003}
+}
+
+@incollection{Exploring_Energy_Performance_TradeOffs,
+year={2006},
+isbn={978-3-540-68039-0},
+booktitle={High Performance Computing - HiPC 2006},
+volume={4297},
+editor={Robert, Yves and Parashar, Manish and Badrinath, Ramamurthy and Prasanna, ViktorK.},
+doi={10.1007/11945918_48},
+title={Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors},
+url={http://dx.doi.org/10.1007/11945918_48},
+publisher={Springer Berlin Heidelberg},
+author={Nagpal, Rahul and Srikant, Y.N.},
+pages={497-508}
+}