X-Git-Url: https://bilbo.iut-bm.univ-fcomte.fr/and/gitweb/mpi-energy2.git/blobdiff_plain/eb119b531613f32cafbcaef136ea9b8c5e8ad1af..64ae1ea15de81e7d26e31750c558df497b58ab44:/Heter_paper.tex?ds=sidebyside

diff --git a/Heter_paper.tex b/Heter_paper.tex
index 8579901..690c6a1 100644
--- a/Heter_paper.tex
+++ b/Heter_paper.tex
@@ -53,7 +53,7 @@
 \newcommand{\Told}{\Xsub{T}{Old}} 
 \begin{document} 
 
-\title{Energy Consumption Reduction in heterogeneous architecture using DVFS}
+\title{Energy Consumption Reduction In a Heterogeneous Architecture Using DVFS}
 
 \author{%
   \IEEEauthorblockN{%
@@ -61,7 +61,7 @@
     RaphaÃ«l Couturier,
     Ahmed Fanfakh and
     Arnaud Giersch
-  }
+  } 
   \IEEEauthorblockA{%
     FEMTO-ST Institute\\
     University of Franche-ComtÃ©\\
@@ -81,13 +81,30 @@
 
 \section{Introduction}
 \label{sec.intro}
-
+Modern processors continue to increased in a performance, achieved  maximum number of floating point operations per second (FLOPS), thus the energy consumption and the heat dissipation are increased drastically  according to this increase. The number of FLOPS is linearly related to power consumption of a CPU~\cite{51}.  
+As an example of more power hungry cluster, according to the Top500 list in June 2014 \cite{43}, Tianhe-2 has more than 3 millions of cores and consumed more  than 17.8 megawatt per second. Moreover, according to the U.S. annual energy outlook 2014 \cite{60}, the price of energy for 1 megawatt per hour is approximately equal to 70\$ (1.16\$ for megawatt per second). Therefore, we can consider the price of the energy consumption for the Tianhe-2 platform is approximately more than 390 millions dollars of megawatt per year. For this reason, the heterogeneous clusters must be offer more energy efficiency due to the increase in the energy cost and the environment influences. Therefore, a green computing clusters are require nowadays.  For example, the GSIC center of Tokyo  heterogeneous cluster became the top of the Green500 list in June 2014 \cite{59}. This platform  has more than four thousand of  MFLOPS per watt. Dynamic voltage and frequency scaling (DVFS) is a process used widely to reduce the energy consumption of the processor. In a heterogeneous clusters enabled DVFS, many researchers used DVFS  in a different ways. DVFS can be minimized the energy consumption but it lead to a disadvantage due to the performance degradation increase. Therefore,  researchers used different optimization strategies to overcame this problem. The best tradeoff relation between the energy reduction and performance degradation ratio is become a key challenges in a heterogeneous platforms. In this paper we are propose a heterogeneous scaling algorithm  that selects the optimal vector of the frequency scaling factors for distributed iterative application, producing minimum energy saving against minimum performance degradation ratio simultaneously. The algorithm has very small overhead, works online and not needs for any training or profiling.  
+
+This paper is organized as follows: Section~\ref{sec.relwork} presents some
+related works from other authors.  Section~\ref{sec.exe} describes how the
+execution time of MPI programs can be predicted.  It also presents an energy
+model for heterogeneous platforms. Section~\ref{sec.compet} presents
+the energy-performance objective function that maximizes the reduction of energy
+consumption while minimizing the degradation of the program's performance.
+Section~\ref{sec.optim} details the proposed heterogeneous scaling algorithm.
+Section~\ref{sec.expe} presents the results of running  the NAS benchmarks on 
+the proposed heterogeneous platform. It also shows the comparison of three different power
+scenarios and it verifies the precision of the proposed algorithm.  Finally, we conclude 
+in Section~\ref{sec.concl} with a summary and some future works.
 
 \section{Related works}
 \label{sec.relwork}
-
-
-
+Energy reduction process for a high performance clusters recently performed using dynamic voltage and frequency scaling (DVFS) technique. DVFS is a technique  enabled in a modern processors to scaled down both of the  voltage and the frequency of the CPU while it is in the computing mode to reduce the energy consumption. DVFS is also  allowed in the graphical processors GPUs, to achieved the same goal. Applying DVFS has a dramatical side effect if it is applied to minimum levels to gain more energy reduction, producing a high percentage of performance degradations for the parallel applications.  Many researchers used different strategies to solve this nonlinear problem for example in~\cite{19,42}, their methods add big overheads to the algorithm to select the
+suitable frequency.  In this paper we  present a method to find the optimal
+set of frequency scaling factors for a heterogeneous cluster to simultaneously optimize both the energy and the execution time  without adding a big overhead.
+This work is developed from our previous work of a homogeneous cluster~\cite{45}. Therefore we are interested to present some works that concerned the heterogeneous clusters enabled DVFS. In general, the heterogeneous cluster works fall into two categorizes: GPUs-CPUs heterogeneous clusters and CPUs-CPUs heterogeneous clusters. In GPUs-CPUs heterogeneous clusters some parallel tasks executed on a GPUs and the others executed on a CPUs. As an example of this works, Luley et al.~\cite{51}, proposed  a heterogeneous cluster composed of Intel Xeon CPUs and NVIDIA GPUs. Their main goal is to determined the energy efficiency as a function of performance per watt, the best tradeoff is done when the performance per watt function is maximized. In the work of Kia Ma et al.~\cite{49}, They developed a scheduling algorithm to distributed different workloads proportional to the computing power of the node to be executed on a CPU or a GPU, emphasize all tasks must be finished in the same time. 
+Recently, Rong et al.~\cite{50}, Their study explain that a heterogeneous clusters enabled DVFS using GPUs and CPUs gave better energy and performance efficiency 
+than other clusters composed of only CPUs. The CPUs-CPUs heterogeneous clusters consist of number of computing nodes  all of the type CPU. Our work in this paper can be classified to this type of the clusters. As an example of this works see  Naveen et al.~\cite{52} work, They developed a policy to dynamically assigned the frequency to a heterogeneous cluster. The goal is to minimizing a fixed metric of $energy*delay^2$. Where our proposed method is automatically optimized  the relation between the energy and the delay of the iterative applications. Other works such as Lizhe et al.~\cite{53}, their algorithm divided the executed tasks into two types: the critical and non critical tasks. The algorithm scaled down the frequency of the non critical tasks as function to the  amount of the slack and communication times that have with maximum of performance degradation percentage of 10\%. In our method there is no fixed bounds for performance degradation percentage and the bound is dynamically computed according to the energy and the performance tradeoff relation of the executed application. 
+There are some approaches used a heterogeneous cluster composed from two different types of Intel and AMD processors such as~\cite{54} and \cite{55}, they predicated  both the energy and the performance for each frequency gear, then the algorithm selected the best gear that gave the best tradeoff. In contrast our algorithm works over a heterogeneous  platform composed of four different types of processors. Others approaches such as \cite{56} and \cite{57}, they are selected the best frequencies for a specified heterogeneous clusters offline using some heuristic methods. While our proposed algorithm works online during the execution time of iterative application. Greedy dynamic approach used by Chen et al.~\cite{58},  minimized the power consumption of a heterogeneous severs  with time/space complexity, this approach had considerable overhead. In our proposed scaling algorithm has very small overhead and it is works without any previous analysis for the application time complexity. 
 
 \section{The performance and energy consumption measurements on heterogeneous architecture}
 \label{sec.exe}
@@ -107,18 +124,19 @@ power (FLOPS), energy consumption, CPU's frequency range, \dots{} but they all
 have the same network bandwidth and latency.
 
 
-\begin{figure}[t]
+
+The  overall execution time  of a distributed iterative synchronous application over a heterogeneous platform  consists of the sum of the computation time and the communication time for every iteration on a node. However, due to the heterogeneous computation power of the computing nodes, slack times might occur when fast nodes have to
+ wait, during synchronous communications, for  the slower nodes to finish  their computations (see Figure~(\ref{fig:heter}). 
+ Therefore,  the overall execution time  of the program is the execution time of the slowest
+ task which have the highest computation time and no slack time.
+  
+ \begin{figure}[t]
   \centering
     \includegraphics[scale=0.6]{fig/commtasks}
   \caption{Parallel tasks on a heterogeneous platform}
   \label{fig:heter}
 \end{figure}
 
- The  overall execution time  of a distributed iterative synchronous application over a heterogeneous platform  consists of the sum of the computation time and the communication time for every iteration on a node. However, due to the heterogeneous computation power of the computing nodes, slack times might occur when fast nodes have to
- wait, during synchronous communications, for  the slower nodes to finish  their computations (see Figure~(\ref{fig:heter})). 
- Therefore,  the overall execution time  of the program is the execution time of the slowest
- task which have the highest computation time and no slack time.
- 
 Dynamic Voltage and Frequency Scaling (DVFS) is a process, implemented in modern processors, that reduces the energy consumption
 of a CPU by scaling down its voltage and frequency.  Since DVFS lowers the frequency of a CPU and consequently its computing power, the execution time of a program running over that scaled down processor might increase, especially if the program is compute bound.  The frequency reduction process can be  expressed by the scaling factor S which is the ratio between  the maximum and the new frequency of a CPU as in EQ (\ref{eq:s}).
 \begin{equation}
@@ -210,8 +228,7 @@ reducing the frequency by a factor of $S$~\cite{3}. Since the FLOPS of a CPU is
 The static power is related to the power leakage of the CPU and is consumed during computation and even when idle. As in~\cite{3,46}, we assume that the static power of a processor is constant during idle and computation periods, and for all its available frequencies. 
 The static energy is the static power multiplied by the execution time of the program. According to the execution time model in EQ(\ref{eq:perf}), 
 the execution time of the program is the summation of the computation and the communication times. The computation time is linearly related  
-to the frequency scaling factor, while this scaling factor does not affect the communication time. The static energy 
-of a processor after scaling its frequency is computed as follows: 
+to the frequency scaling factor, while this scaling factor does not affect the communication time. The static energy of a processor after scaling its frequency is computed as follows: 
 \begin{equation}
   \label{eq:Estatic}
  E_\textit{s} = P_\textit{s} \cdot (Tcp \cdot S  + Tcm)
@@ -261,7 +278,7 @@ In the same way, we normalize the energy by computing the ratio between the cons
   E_\textit{Norm} = \frac{E_\textit{Reduced}}{E_\textit{Original}} \\
   {} = \frac{ \sum_{i=1}^{N}{(S_i^{-2} \cdot Pd_i \cdot  Tcp_i)} +
  \sum_{i=1}^{N} {(Ps_i \cdot T_{New})}}{\sum_{i=1}^{N}{( Pd_i \cdot  Tcp_i)} +
- \sum_{i=1}^{N} {(Ps_i@+eYd162 \cdot T_{Old})}}
+ \sum_{i=1}^{N} {(Ps_i \cdot T_{Old})}}
 \end{multline} 
 Where $T_{New}$ and $T_{Old}$ are computed as in EQ(\ref{eq:pnorm}).
 
@@ -272,11 +289,6 @@ scaling factors $S_1,S_2,\dots,S_N$ reduce both the energy and the execution
 time simultaneously.  But the main objective is to produce maximum energy
 reduction with minimum execution time reduction.  
 
-Many researchers used different strategies to solve this nonlinear problem for example
-in~\cite{19,42}, their methods add big overheads to the algorithm to select the
-suitable frequency.  In this paper we  present a method to find the optimal
-set of frequency scaling factors to simultaneously optimize both energy and execution time
- without adding a big overhead. \textbf{put the last two phrases in the related work section}
  
   
 Our solution for this problem is to make the optimization process for energy and execution time follow the same
@@ -425,7 +437,7 @@ To evaluate the efficiency and the overall energy consumption reduction of algor
 \cite{44}. The experiments were executed on the simulator SimGrid/SMPI
 v3.10~\cite{casanova+giersch+legrand+al.2014.versatile} which offers easy tools to create a heterogeneous platform and run message passing applications over it. The heterogeneous platform that was used in the experiments, had one core per node because just one process was executed per node. The heterogeneous platform  was composed of four types of nodes. Each type of nodes had different characteristics such as the maximum CPU frequency, the number of
 available frequencies and the computational power, see table
-(\ref{table:platform}). The characteristics of these different types of  nodes are inspired   from the specifications of real Intel processors. The heterogeneous platform had up to 144 nodes and had nodes from the four types in equal proportions, for example if  a benchmark was executed on 8 nodes, 2 nodes from each type were used. Since the constructors of CPUs do not specify the dynamic and the static power of their CPUs, for each type of node they were chosen proportionally to  its computing power (FLOPS).  In the initial heterogeneous platform,  while computing with highest frequency, each node  consumed power proportional to its computing power which 80\% of it was dynamic power and the rest was 20\% was static power, the same assumption  was made in \cite{45,3}. Finally, These nodes were connected via an ethernet network with 1 Gbit/s bandwidth.
+(\ref{table:platform}). The characteristics of these different types of  nodes are inspired   from the specifications of real Intel processors. The heterogeneous platform had up to 144 nodes and had nodes from the four types in equal proportions, for example if  a benchmark was executed on 8 nodes, 2 nodes from each type were used. Since the constructors of CPUs do not specify the dynamic and the static power of their CPUs, for each type of node they were chosen proportionally to  its computing power (FLOPS).  In the initial heterogeneous platform,  while computing with highest frequency, each node  consumed power proportional to its computing power which 80\% of it was dynamic power and the rest was 20\% for the static power, the same assumption  was made in \cite{45,3}. Finally, These nodes were connected via an ethernet network with 1 Gbit/s bandwidth.
 
 
 \begin{table}[htb]
@@ -662,7 +674,7 @@ section, these ratios are changed and two new power scenarios are considered in
 \end{itemize}
 The NAS parallel benchmarks were executed again over processors that follow the the new power scenarios. The class C of each benchmark was run over 8 or 9 nodes and the results are presented in  tables (\ref{table:res_s1} and \ref{table:res_s2}). \textbf{These tables show that the energy saving percentage of the 70\%-30\% scenario is less for all benchmarks compared to the energy saving of the 90\%-10\% scenario, because this scenario uses higher percentage of dynamic dynamic power that is quadratically related to scaling factors. While the performance degradation percentage is less in 70\%-30\% scenario  compared to 90\%-10\%  scenario, because the first scenario used higher percentage for static power consumption that is linearly related to scaling factors and thus the execution time. }
 
-The two new power scenarios are compared to the old one  in figure (\ref{fig:sen_comp}). It shows the average of the performance degradation, the energy saving and the distances for all NAS benchmarks of class C running on 8 or 9 nodes. The comparison shows that  the energy saving ratio is proportional to the dynamic power ratio: it is increased when applying the  90\%-10\% scenario because at maximum frequency the dynamic  energy is the the most relevant in the overall consumed energy and can be reduced by lowering the frequency of some processors. On the other hand, the energy saving is decreased when  the 70\%-30\% scenario is used because the dynamic  energy is less relevant in the overall consumed energy and lowering the frequency do not returns big energy savings.
+The two new power scenarios are compared to the old one in figure (\ref{fig:sen_comp}). It shows the average of the performance degradation, the energy saving and the distances for all NAS benchmarks of class C running on 8 or 9 nodes. The comparison shows that  the energy saving ratio is proportional to the dynamic power ratio: it is increased when applying the  90\%-10\% scenario because at maximum frequency the dynamic  energy is the the most relevant in the overall consumed energy and can be reduced by lowering the frequency of some processors. On the other hand, the energy saving is decreased when  the 70\%-30\% scenario is used because the dynamic  energy is less relevant in the overall consumed energy and lowering the frequency do not returns big energy savings.
 Moreover, the average of the performance degradation is decreased when using a higher ratio for static power (e.g. 70\%-30\% scenario and 80\%-20\% scenario). Since the proposed algorithm optimizes the energy consumption when using a higher ratio for dynamic power the algorithm selects bigger frequency scaling factors that result in more energy saving but less performance, for example see the figure (\ref{fig:scales_comp}). The opposite happens when using a higher ratio for  static  power, the algorithm proportionally  selects  smaller scaling values which results in less energy saving but less performance degradation. 
 
 
