Related Works

diff --git a/Heter_paper.tex b/Heter_paper.tex
index 8579901ce75d38848ba94132c1c5ba799628ffe9..23ea28d7993297251bdf287cf9428e85185f184b 100644 (file)
--- a/Heter_paper.tex
+++ b/Heter_paper.tex
@@ -53,7 +53,7 @@
 \newcommand{\Told}{\Xsub{T}{Old}} 
 \begin{document} 
 
 \newcommand{\Told}{\Xsub{T}{Old}} 
 \begin{document} 
 

-\title{Energy Consumption Reduction in heterogeneous architecture using DVFS}
+\title{Energy Consumption Reduction In a Heterogeneous Architecture Using DVFS}

 
 \author{%
   \IEEEauthorblockN{%
 
 \author{%
   \IEEEauthorblockN{%


@@ -61,7 +61,7 @@
     Raphaël Couturier,
     Ahmed Fanfakh and
     Arnaud Giersch
     Raphaël Couturier,
     Ahmed Fanfakh and
     Arnaud Giersch

-  }
+  } 

   \IEEEauthorblockA{%
     FEMTO-ST Institute\\
     University of Franche-Comté\\
   \IEEEauthorblockA{%
     FEMTO-ST Institute\\
     University of Franche-Comté\\


@@ -85,9 +85,13 @@
 
 \section{Related works}
 \label{sec.relwork}
 
 \section{Related works}
 \label{sec.relwork}

-
-
-
+Energy reduction process for a high performance clusters recently performed using dynamic voltage and frequency scaling (DVFS) technique. DVFS is a technique  enabled in a modern processors to scaled down both of the  voltage and the frequency of the CPU while it is in the computing mode to reduce the energy consumption. DVFS is also  allowed in the graphical processors GPUs, to achieved the same goal. Applying DVFS has a dramatical side effect if it is applied to minimum levels to gain more energy reduction, producing a high percentage of performance degradations for the parallel applications.  Many researchers used different strategies to solve this nonlinear problem for example in~\cite{19,42}, their methods add big overheads to the algorithm to select the
+suitable frequency.  In this paper we  present a method to find the optimal
+set of frequency scaling factors for a heterogeneous cluster to simultaneously optimize both the energy and the execution time  without adding a big overhead.
+This work is developed from our previous work of a homogeneous cluster~\cite{45}. Therefore we are interested to present some works that concerned the heterogeneous clusters enabled DVFS. In general, the heterogeneous cluster works fall into two categorizes: GPUs-CPUs heterogeneous clusters and CPUs-CPUs heterogeneous clusters. In GPUs-CPUs heterogeneous clusters some parallel tasks executed on a GPUs and the others executed on a CPUs. As an example of this works, Luley et al.~\cite{51}, proposed  a heterogeneous cluster composed of Intel Xeon CPUs and NVIDIA GPUs. Their main goal is to determined the energy efficiency as a function of performance per watt, the best tradeoff is done when the performance per watt function is maximized. In the work of Kia Ma et al.~\cite{49}, They developed a scheduling algorithm to distribute different workloads proportional to the computing power of the node to be executed on a CPU or a GPU, emphasize all tasks must be finished in the same time. 
+Recently, Rong et al.~\cite{50}, Their study explain that a heterogeneous clusters enabled DVFS using GPUs and CPUs gave better energy and performance efficiency 
+than other clusters composed of only CPUs. The CPUs-CPUs heterogeneous clusters consist of number of computing nodes  all of the type CPU. Our work in this paper can be classified to this type of the clusters. As an example of this works see  Naveen et al.~\cite{52} work, They developed a policy to dynamically assigned the frequency to a heterogeneous cluster. The goal is to minimizing a fixed metric of $energy*delay^2$. Where our proposed method is automatically optimized  the relation between the energy and the delay of the iterative applications. Other works such as Lizhe et al.~\cite{53}, their algorithm divided the executed tasks into two types: the critical and non critical tasks. The algorithm scaled down the frequency of the non critical tasks as function to the  amount of the slack and communication times that have with maximum of performance degradation percentage of 10\%. In our method there is no fixed bounds for performance degradation percentage and the bound is dynamically computed according to the energy and the performance tradeoff relation of the executed application. 
+There are some approaches used a heterogeneous cluster composed from two different types of Intel and AMD processors such as~\cite{54} and \cite{55}, they predicated  both the energy and the performance for each frequency gear, then the algorithm selected the best gear that gave the best tradeoff. In contrast our algorithm works over a heterogeneous  platform composed of four different types of processors. Others approaches such as \cite{56} and \cite{57}, they are selected the best frequencies for a specified heterogeneous clusters offline using some heuristic methods. While our proposed algorithm works online during the execution time of iterative application. Greedy dynamic approach used by Chen et al.~\cite{58},  minimized the power consumption of a heterogeneous severs  with time/space complexity, this approach had considerable overhead. In our proposed scaling algorithm has very small overhead and it is works without any previous analysis for the application time complexity. 

 
 \section{The performance and energy consumption measurements on heterogeneous architecture}
 \label{sec.exe}
 
 \section{The performance and energy consumption measurements on heterogeneous architecture}
 \label{sec.exe}


@@ -107,18 +111,19 @@ power (FLOPS), energy consumption, CPU's frequency range, \dots{} but they all
 have the same network bandwidth and latency.
 
 
 have the same network bandwidth and latency.
 
 

-\begin{figure}[t]
+
+ The  overall execution time  of a distributed iterative synchronous application over a heterogeneous platform  consists of the sum of the computation time and the communication time for every iteration on a node. However, due to the heterogeneous computation power of the computing nodes, slack times might occur when fast nodes have to
+ wait, during synchronous communications, for  the slower nodes to finish  their computations (see Figure~(\ref{fig:heter}). 
+ Therefore,  the overall execution time  of the program is the execution time of the slowest
+ task which have the highest computation time and no slack time.
+  
+ \begin{figure}[t]

   \centering
     \includegraphics[scale=0.6]{fig/commtasks}
   \caption{Parallel tasks on a heterogeneous platform}
   \label{fig:heter}
 \end{figure}
 
   \centering
     \includegraphics[scale=0.6]{fig/commtasks}
   \caption{Parallel tasks on a heterogeneous platform}
   \label{fig:heter}
 \end{figure}
 

- The  overall execution time  of a distributed iterative synchronous application over a heterogeneous platform  consists of the sum of the computation time and the communication time for every iteration on a node. However, due to the heterogeneous computation power of the computing nodes, slack times might occur when fast nodes have to
- wait, during synchronous communications, for  the slower nodes to finish  their computations (see Figure~(\ref{fig:heter})). 
- Therefore,  the overall execution time  of the program is the execution time of the slowest
- task which have the highest computation time and no slack time.
- 

 Dynamic Voltage and Frequency Scaling (DVFS) is a process, implemented in modern processors, that reduces the energy consumption
 of a CPU by scaling down its voltage and frequency.  Since DVFS lowers the frequency of a CPU and consequently its computing power, the execution time of a program running over that scaled down processor might increase, especially if the program is compute bound.  The frequency reduction process can be  expressed by the scaling factor S which is the ratio between  the maximum and the new frequency of a CPU as in EQ (\ref{eq:s}).
 \begin{equation}
 Dynamic Voltage and Frequency Scaling (DVFS) is a process, implemented in modern processors, that reduces the energy consumption
 of a CPU by scaling down its voltage and frequency.  Since DVFS lowers the frequency of a CPU and consequently its computing power, the execution time of a program running over that scaled down processor might increase, especially if the program is compute bound.  The frequency reduction process can be  expressed by the scaling factor S which is the ratio between  the maximum and the new frequency of a CPU as in EQ (\ref{eq:s}).
 \begin{equation}


@@ -272,11 +277,6 @@ scaling factors $S_1,S_2,\dots,S_N$ reduce both the energy and the execution
 time simultaneously.  But the main objective is to produce maximum energy
 reduction with minimum execution time reduction.  
 
 time simultaneously.  But the main objective is to produce maximum energy
 reduction with minimum execution time reduction.  
 

-Many researchers used different strategies to solve this nonlinear problem for example
-in~\cite{19,42}, their methods add big overheads to the algorithm to select the
-suitable frequency.  In this paper we  present a method to find the optimal
-set of frequency scaling factors to simultaneously optimize both energy and execution time
- without adding a big overhead. \textbf{put the last two phrases in the related work section}

  
   
 Our solution for this problem is to make the optimization process for energy and execution time follow the same
  
   
 Our solution for this problem is to make the optimization process for energy and execution time follow the same


@@ -662,7 +662,7 @@ section, these ratios are changed and two new power scenarios are considered in
 \end{itemize}
 The NAS parallel benchmarks were executed again over processors that follow the the new power scenarios. The class C of each benchmark was run over 8 or 9 nodes and the results are presented in  tables (\ref{table:res_s1} and \ref{table:res_s2}). \textbf{These tables show that the energy saving percentage of the 70\%-30\% scenario is less for all benchmarks compared to the energy saving of the 90\%-10\% scenario, because this scenario uses higher percentage of dynamic dynamic power that is quadratically related to scaling factors. While the performance degradation percentage is less in 70\%-30\% scenario  compared to 90\%-10\%  scenario, because the first scenario used higher percentage for static power consumption that is linearly related to scaling factors and thus the execution time. }
 
 \end{itemize}
 The NAS parallel benchmarks were executed again over processors that follow the the new power scenarios. The class C of each benchmark was run over 8 or 9 nodes and the results are presented in  tables (\ref{table:res_s1} and \ref{table:res_s2}). \textbf{These tables show that the energy saving percentage of the 70\%-30\% scenario is less for all benchmarks compared to the energy saving of the 90\%-10\% scenario, because this scenario uses higher percentage of dynamic dynamic power that is quadratically related to scaling factors. While the performance degradation percentage is less in 70\%-30\% scenario  compared to 90\%-10\%  scenario, because the first scenario used higher percentage for static power consumption that is linearly related to scaling factors and thus the execution time. }
 

-The two new power scenarios are compared to the old one  in figure (\ref{fig:sen_comp}). It shows the average of the performance degradation, the energy saving and the distances for all NAS benchmarks of class C running on 8 or 9 nodes. The comparison shows that  the energy saving ratio is proportional to the dynamic power ratio: it is increased when applying the  90\%-10\% scenario because at maximum frequency the dynamic  energy is the the most relevant in the overall consumed energy and can be reduced by lowering the frequency of some processors. On the other hand, the energy saving is decreased when  the 70\%-30\% scenario is used because the dynamic  energy is less relevant in the overall consumed energy and lowering the frequency do not returns big energy savings.
+The two new power scenarios are compared to the old one in figure (\ref{fig:sen_comp}). It shows the average of the performance degradation, the energy saving and the distances for all NAS benchmarks of class C running on 8 or 9 nodes. The comparison shows that  the energy saving ratio is proportional to the dynamic power ratio: it is increased when applying the  90\%-10\% scenario because at maximum frequency the dynamic  energy is the the most relevant in the overall consumed energy and can be reduced by lowering the frequency of some processors. On the other hand, the energy saving is decreased when  the 70\%-30\% scenario is used because the dynamic  energy is less relevant in the overall consumed energy and lowering the frequency do not returns big energy savings.

 Moreover, the average of the performance degradation is decreased when using a higher ratio for static power (e.g. 70\%-30\% scenario and 80\%-20\% scenario). Since the proposed algorithm optimizes the energy consumption when using a higher ratio for dynamic power the algorithm selects bigger frequency scaling factors that result in more energy saving but less performance, for example see the figure (\ref{fig:scales_comp}). The opposite happens when using a higher ratio for  static  power, the algorithm proportionally  selects  smaller scaling values which results in less energy saving but less performance degradation. 
 
 
 Moreover, the average of the performance degradation is decreased when using a higher ratio for static power (e.g. 70\%-30\% scenario and 80\%-20\% scenario). Since the proposed algorithm optimizes the energy consumption when using a higher ratio for dynamic power the algorithm selects bigger frequency scaling factors that result in more energy saving but less performance, for example see the figure (\ref{fig:scales_comp}). The opposite happens when using a higher ratio for  static  power, the algorithm proportionally  selects  smaller scaling values which results in less energy saving but less performance degradation. 
 
 

diff --git a/my_reference.bib b/my_reference.bib
index a968a066f5134c386715fe8489363833e3bcc79c..e7163036c5432ea6e1f090b1403c975c9e5030d3 100644 (file)
--- a/my_reference.bib
+++ b/my_reference.bib
@@ -648,7 +648,7 @@ ISSN={0278-0070}
   year = 2014,
   month = oct,
   doi = {10.1016/j.jpdc.2014.06.008},
   year = 2014,
   month = oct,
   doi = {10.1016/j.jpdc.2014.06.008},

-  pdf = {http://hal.inria.fr/docs/01/05/75/41/PDF/simgrid3-journal.pdf},
+  pdf = {http://hal.inria.fr/docs/01/05/75/41/PDF/simgrid3-journal.pdf}

 }
 
 @article{46,
 }
 
 @article{46,


@@ -679,10 +679,128 @@ ISSN={0278-0070}
 
 @techreport{48,
        title = {Energy efficiency evaluation and benchmarking of {AFRL}'s Condor high performance computer},
 
 @techreport{48,
        title = {Energy efficiency evaluation and benchmarking of {AFRL}'s Condor high performance computer},

-       url = {http://oai.dtic.mil/oai/oai?verb=getRecord&metadataPrefix=html&identifier=ADA548738},
+       

        urldate = {2014-10-16},
        institution = {{DTIC} Document},
        author = {Luley, Ryan and Usmail, Courtney and Barnell, Mark},
        year = {2011},
        file = {a548738.pdf:files/30/a548738.pdf:application/pdf}
        urldate = {2014-10-16},
        institution = {{DTIC} Document},
        author = {Luley, Ryan and Usmail, Courtney and Barnell, Mark},
        year = {2011},
        file = {a548738.pdf:files/30/a548738.pdf:application/pdf}

-}
\ No newline at end of file
+}
+
+@INPROCEEDINGS{49, 
+author={Kai Ma and Xue Li and Wei Chen and Chi Zhang and Xiaorui Wang}, 
+booktitle={Parallel Processing (ICPP), 2012 41st International Conference on}, 
+title={GreenGPU: A Holistic Approach to Energy Efficiency in GPU-CPU Heterogeneous Architectures}, 
+year={2012}, 
+month={Sept}, 
+pages={48-57}, 
+keywords={energy consumption;graphics processing units;parallel architectures;AMD Phenom II CPU;CUDA framework;GPU-CPU heterogeneous architectures;GreenGPU;Nvidia GeForce GPU;energy consumption;energy efficiency;high performance computing;holistic approach;Algorithm design and analysis;Computer architecture;Frequency conversion;Graphics processing unit;Green products;Heuristic algorithms;Time frequency analysis;GPU;dynamic frequency scaling;energy efficiency;workload division}, 
+doi={10.1109/ICPP.2012.31}, 
+ISSN={0190-3918}
+}
+
+
+
+@INPROCEEDINGS{50, 
+author={Rong Ge and Vogt, R. and Majumder, J. and Alam, A. and Burtscher, M. and Ziliang Zong}, 
+booktitle={Parallel Processing (ICPP), 2013 42nd International Conference on}, 
+title={Effects of Dynamic Voltage and Frequency Scaling on a K20 GPU}, 
+year={2013}, 
+month={Oct}, 
+pages={826-833}, 
+keywords={energy conservation;graphics processing units;parallel processing;power aware computing;power consumption;DVFS schedulers;GPU computing;K20 GPU;Nvidia K20c Kepler GPU;application performance;compute-bound high-performance workloads;dual Intel Sandy Bridge CPU;dynamic voltage and frequency scaling;energy efficiency;high-throughput workloads;power consumption;power-aware heterogeneous system;Benchmark testing;Computer architecture;Energy consumption;Graphics processing units;Market research;Measurement;Power demand;DVFS in GPU Computing;Dynamic Voltage and Frequency Scaling;Energy-Efficient Computing}, 
+doi={10.1109/ICPP.2013.98}, 
+ISSN={0190-3918}
+}
+
+
+@techreport{51,
+       title = {Energy efficiency evaluation and benchmarking of {AFRL}'s Condor high performance computer},
+       
+       urldate = {2014-10-16},
+       institution = {{DTIC} Document},
+       author = {Luley, Ryan and Usmail, Courtney and Barnell, Mark},
+       year = {2011},
+       file = {a548738.pdf:files/30/a548738.pdf:application/pdf}
+}
+
+
+
+@INPROCEEDINGS{52,
+author = {Naveen Muralimanohar and Karthik Ramani and Rajeev Balasubramonian},
+title = {Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity},
+booktitle = {In Proceedings of ISPASS},
+year = {2006}
+}
+
+@article{53,
+title = "Energy-aware parallel task scheduling in a cluster ",
+journal = "Future Generation Computer Systems ",
+volume = "29",
+number = "7",
+pages = "1661 - 1670",
+year = "2013",
+issn = "0167-739X",
+doi = "http://dx.doi.org/10.1016/j.future.2013.02.010",
+url = "http://www.sciencedirect.com/science/article/pii/S0167739X13000484",
+author = {Lizhe Wang and Samee U. Khan and Dan Chen and Joanna Kołodziej and Rajiv Ranjan and Cheng-zhong Xu and Albert Zomaya}
+
+
+}
+
+
+
+@article{54,
+       title = {Blackbox prediction of the impact of {DVFS} on end-to-end performance of multitier systems},
+       volume = {37},
+       url = {http://dl.acm.org/citation.cfm?id=1773404},
+       number = {4},
+       urldate = {2014-03-28},
+       journal = {{ACM} {SIGMETRICS} Performance Evaluation Review},
+       author = {Joshi, Kaustubh R. and Hiltunen, Matti A. and Schlichting, Richard D. and Sanders, William H.},
+       year = {2010},
+       pages = {59--63}
+}
+
+
+@INPROCEEDINGS{55, 
+author={Spiliopoulos, V. and Kaxiras, S. and Keramidas, G.}, 
+booktitle={Green Computing Conference and Workshops (IGCC), 2011 International}, 
+title={Green governors: A framework for Continuously Adaptive DVFS}, 
+year={2011}, 
+month={July}, 
+pages={1-8}, 
+doi={10.1109/IGCC.2011.6008552}
+}
+
+
+@proceedings{56,
+  author = {Shelepov, D. and Fedorova, A.},
+  intrahash = {2287b0be888deceb937bace77634081a}, 
+  organization = {Workshop on the Interaction between Operating Systems and Computer Architecture, in conjunction with ISCA},
+  timestamp = {2008-10-07T16:32:27.000+0200},
+  title = {Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures},
+  year = {2008}
+}
+
+
+@article{57,
+       title = {Minimizing Energy Consumption for Frame-Based Tasks on Heterogeneous Multiprocessor Platforms},
+       url = {http://www.cis.temple.edu/~wu/research/publications/Publication_files/TPDS14-LDW.pdf},
+       year={2014},
+       author = {Li, Dawei and Wu, Jie}
+}
+
+@article{58,
+       title = {Dynamic frequency scaling schemes for heterogeneous clusters under quality of service requirements},
+       volume = {28},
+       url = {http://www.tik.ee.ethz.ch/file/6b2639d5dad0cd754d723ba0eb92cbf6/201211_06.pdf},
+       number = {6},
+       urldate = {2014-11-07},
+       journal = {Journal of Information Science and Engineering},
+       author = {Chen, Jian-Jia and Huang, Kai and Thiele, Lothar},
+       year = {2012},
+       pages = {1073--1090}
+       
+}
+