\textit{Chaotic Systems} are interests theory to generate random number. Here, the use of this theory has been increase  due to the sensitivity to initial conditions, unpredictability and ability to reciprocal synchronization. However, the finite precision of arithmetic and quantization generate a non-ideal and periodic random number. We can found chaotic PRNG proposed by using a differential equations in a continuous time domain. In other side, the most chaotic PRNG are implemented based on the recurrent sequences using chaotic maps in a discrete time domain $x^{0} \in R$ where $x^{n+1} = \ f(x^{n})$. Hence, from the cryptographer’s point of view, the most essential drawbacks of the chaotic systems are: weak resistance to recovery of parameters, relatively low digital precision comparing to the analog generators, periodicity problems, non ideal probability distributions, higher level of correlation and suffer from serious dynamical degradation due to quantization error and finite representation of system states, including loss of periodicity and shorter pseudo-orbits.
  
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\textit{Chaotic Map Generators} describe here are a generators based on a polynomial mapping that is equivalent to recurrence matrix degree 2. Here, the chaotic map generators uses a non-linear dynamic transformation. For this survey we found a logistic map based on this equation of  $x_{t+1} = rx_{t} \ (1− x_{t})$, where r is what called the \emph{biotic potential} $(3,57 \ < r \ < \ 4,0)$. Also, there is H$\acute{e}$non map which is also a discrete-time dynamical system according to the equations of $x_{t+1} = y_{t} + (1 - \ a x_t^2)$ and $y_{t+1}= \ bx_{t+1}$, where "a" and "b" are called \emph{canonical parameters}. Following that, a chaotic map PRNG is implemented on FPGA and presented in in \cite{6868789}. Here, the authors start from earlier study done of some FPGA implementation of thous chaotic map PRNG  and presented in \cite{dabal2011chaos} and \cite{dabal2012fpga}. The authors implement two new optimization version of PRNG based on chaotic logistic map using the XSG Xilinx tool for more HW optimization. The first is a log-LUT based on LUT blocs and a high-speed carry line of the FPGA. Then, the second is Log-DSP that use directly DSP component of FPGA. However, they add delays to ensure parallel sequence generation and a complex initial sequence used for a better NIST test results.

Another work presented in \cite{merahcoupling}, where the authors demonstrate a mixed version using tow chaotic map to increase the security level against plaintex attacks. They show by coupling a chaotic encryption system (ENS) based on 2-D H$\acute{e}$non map and control system (CRS) based on 1-D logistic map. The ENS is used to generate the chaotic sequence, and the CSR to control the multiplexer and choose the outputs bits of ENS according to the value generated by the logistic map. Here, the final outputs bits are the XOR of the MSB of 32-bit CSR with his neighbor LSB following some rules. In the same approach and in \cite{hariprasad2013fpga}, the authors uses a chaotic logistic map to generate output. They increase the period by a reseeding module, where the output sequence will be XORed with a vector mixing module based on auxiliary linear generator. Another solution proposed in \cite{5554284}, where the authors presents a chaos system based on three dynamic nonlinear transform arithmetic DNT process. It's a parallel structure that transform an input 3 times and improve a high cycle-length and distribution output sequence. However, for each DNT module it initiates his 2x256 code book and obtain the binary input sequence. Then, transformed and look up it using the inputs as parameters $x_{t+1}= \ x_{t} \ (C(w)\ R(q))$. 

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\textit{Spationtemporal Chaos Geneators} are a temporally chaotic system as for a chaotic map. It's also a spatially and there is many mathematical models can be use to represent this type of generator. In \cite{mao2006design} and to achieve a high operation speed, a bi-directional coupled chaotic map lattices (CML) has been used as a models represented by $x_{t+1}(i) = (1- \epsilon) f(x_{t}(i) \ + \ \frac{\epsilon}{2} (f(x_{t}(i-1) \ + \ f(x_{n}(i+1)$, where n and i are respectively temporal and spatial indexes of discrete lattices. $\epsilon$ is the couple coefficient, L is the number of the total spatial lattices and f(x) is a logistic map. They first deal with continuous domain with digitized all operand to be suited for HW implementation by using and modifying the CML to a finite integer set. Then second and to avoid finite precision chaotic map problem, they compute only the insignificant bit is subject to be an output.  
 
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\textit{Fibonacci post-processing Generators} presented in \cite{mansingka2013fibonacci}. It's uses a non-autonomous 4D hyperchaotic-based PRNG post processing based on Fibonacci series and driven by a 256-bit LFSR. The post processing is based on two loop feedback, where in first loop, they use a fixed 1-bit static rotation to suppress the short-term predictability. Then, the second loop is based on a variable rotation controlled using Fibonacci series of K-bit to enhances differential sensitivity if there is a change at any bit when the other bit propagate during n-cycle.

\textit{Chaotic Iteration} or CI has been proposed by the authors in \cite{fang2014fpga} \cite{bahi2013fpga} to implement a new post processing with the same chaotic theory characteristic defined by Devaney, Li-Yorke, to give better statistic test and increase cryptography. However, they claim their chaotic iterations generate a set of vectors (Boolean) and they are defined by an initial state $x^{0}$, an iteration function f, and a strategy S said to be a \emph{chaotic strategy}. Where, at the n-th iteration, only the $S^{n}-th$ cell is \emph{iterated}. Note that in a more general formulation, $S^{n}$ can be a subset of components and $f((x^{n-1})_{S^{n}})$ can be replaced by $f((x^{n})_{S^{n}})$ , where $k < n$, describing for example delays transmission. The main requirement is to prevent the machine from working in silos, by taking at each iterate a new input from the outside world. By doing so, the finite state machine does not necessarily enter into a loop: a same state can be visited twice, but with two completely different future evolution, depending on the inputs the machine receive. Over four version proposed, one of them has been implemented on FPGA using Chaotic iteration as post processing which use a BBS and XORshift PRNG as generator. The internal state x is a vector of 16-bits, whereas two 64-bit XORshift generators are provided as entropy sources and then the outputs are spread into four 32-bit integers. Then for each integer, there are 16 (2-bits) components that can be found and every 12 of these components are used to update the states. Lastly, the 4 least significant bits (LSBs) of the output BBS generator decide if the state must be updated with the considered 13-bits block or not.