\textit{Linear Feedback Shift Register Generators} or LFSR use a feedback polynomial driven by an exclusive-OR (XOR) as a coefficients to shift bits of the register based on Flip-Flop. It uses an initial input called "seed" and a n-bits generation period of $2^{n}-1$. However, even there are many FPGA implementation of LFSR can be founded, few of them has a optimize version on FPGA. As in this work \cite{6614692}, where the authors present two types of PRNG based LFSR. The first is called \emph{Shrinking Generator} (SG), that uses two LFSRs of $67-bit$. It consist for every clock cycle, the bit output generated will be the same of the second LFSR-2 if the 1-bits LSB of the first LFSR-1  is "1" or put "0". The second PRNG is called \emph{alternating step generator} (ASG). It uses a third LFSR-3 of $141-bits$ to control which bit output will be token from the others two LFSR of $131 and 137bit$. However, for a small comparison purpose, the SG has a Total period of $L_{T}= \ (2^{L_{2}-1})*2^{L_{1}-1}$, where the ASG has a period of $L_{T}= \ 2^{L_{1}}(2^{L_{2}-1})(2^{L_{3}-1})$. 
 
\textit{Linear Congruential Generators} or LCG are another linear recurrence described by $x_{i+1} = (ax_{i} + b) \ mod \ 2^{n}$, and "a" is called the multiplier, "b" the increment, and "m" the modulus. A FPGA implementation of LCG can be demonstrated in \cite{katti2009efficient}, where the authors propose  two version of PRNG based LCG. The first version is a \emph{coupled LCG} (CLCG), coupling two linear congruential generator. It consists the use of the first LCG-1 to generate a control bit, and to select the output bit from the second LCG-2 following this equation $x_{t+1} = (a_{1} × x_{t} + b_{1}) \ mod \ 2^{n}$. However, the second version is a 4-stages pipeline of two CLCG that can generate a 4-bit simultaneous. As a consequences and for every pipeline level, a n-bit/n-pipeline will be computed with a two n-bit additions generated by the flowing equation $x_{t+1} = (2^{r} * x_{t} \ mod \ 2^{n}) + (x_{i} + b_{1}) \ mod \ 2^{n})$. The results of every stage will be feedback and processed in the earlier and following stage for more complexity.

\textit{LUT and Accumulator Generators} are a digital component used or implemented on FPGA to accelerate hardware optimization. The \emph{Lookup-Tables} are a fully dependent FPGA technologies vendors. Every configurable logic block (CLB) of FPGA include a n-Look-up Table (LUT 2/4/6/8-inputs and one outputs), some carry, a control logic and storage elements. In the other side, the \emph{accumulators} are an user combinatory logic circuit that uses the FPGA resources as a components. Some of the works based on LUT are cited in \cite{thomas2008fpga}, \cite{thomas2010fpga} and \cite{thomas2013lut}. The authors of thous papers presents a series of a LUT optimized PRNG based on F-2 linear matrix recursive algorithms. The basic idea is to provide a maximum area efficiency using thous optimization. As consequences and for each row of the recurrence matrix "A" mapped as a XOR gate, can also be implemented in a single LUT. Also,  it's allow in the same time, the test of the characteristic polynomial of each matrix for primitivity. Thous PRNGs proposed as LFSR or \emph{masterine tewister MT} will use the LUT as a Flip-Flips (FF), Shift Registers (SR) or block of RAMs and then compare between them in FPGA. However, the big drawback of this method (LUT) is when creating a long period sequence. To do that, a large number of LUT (FF, SR, RAM) pairs must be used. Even if an application only needs 64 bits per cycle, it must use 512 LUT-FFs to get a period of $2^{512-1}$ for example. Even that, the authors claim a 87 percent the performance will be wasted using this optimization. 

Another implementation in \cite{gonzalez2011pseudorandom}, where the authors propose a 9-stage PRNG of 8 bit using digital accumulator. Here, it based on $\sum \Delta$ modulators M for fractional frequency synthesizers and implemented as self-recursive structure. They claims by taking a constant X as an inputs, the accumulator sum P0 is the state variable of the system. Then and for every cycle, two outputs are generated, the sum modulus of M or the \emph{quantization error} e0 $P0[i]= \ X \ + e0[i-1]$ and the carry output y0 for overloads if the $sum >= M$. However, the proposal solution implement a multistage of  $\sum \Delta$, where the previews stage of the accumulator and the output M will be feedback to the early stage. Also, the authors scale the error e0 by a coefficient inputs accumulator and multiplied by a binary variable $d \in {0, 1}$ generated by a linear feedback shift register (LFSR).