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-\subsubsection{CPU Power impacts on performance\\}
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-\begin{table} [htbp]
-\centering
-\begin{tabular}{r c }
- \hline
- Grid architecture & 2 $\times$ 16\\ %\hline
- Inter Network & N2 : $bw$=1Gbs - $lat$=5.10$^{-5}$ \\ %\hline
- Input matrix size & $N_{x} = 150 \times 150 \times 150$\\
- CPU Power & From 3 to 19 GFlops \\ \hline
- \end{tabular}
-\caption{Test conditions: CPU Power impacts}
-\label{tab:06}
-\end{table}
-
-\begin{figure} [ht!]