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\chapter{Parallel Architectures and  Iterative Applications}
\label{ch1}
%% Introduction
%\lettrine[lines=2]{A}{u} 

\section{Introduction}
\label{ch1:1}

Most of the software applications are structured as sequential programs.
The structure of the program code is  a series of instructions that
are executed successively one after the other. For many years until a short time,
with each new generation of microprocessors,  users of  sequential applications expected that these applications should run faster over them than over the previous ones.
Nowadays, this idea is no longer valid  since  recent releases of  microprocessors have many computing units that are embedded in one chip and  programs are  running  only over one computing unit sequentially.
Indeed, new applications have significantly improved  their performance over  new architectures in parallel compared to traditional applications.
To improve the performance  of  applications, they should be parallelized  and executed simultaneously over all available computing units. 
Moreover, parallel applications should be optimized to the  parallel  hardwares that  will execute them. 
Therefore, parallel applications and parallel architectures are closely tied together. 
For example, the energy consumption of one parallel system mainly depends on both: (1) parallel applications and (2) parallel architectures. Indeed, an energy consumption model or any measurement system depends on many specifications, some of them are related to the  parallel hardware features such as: (1) the frequency of  processor, (2) the  power consumption of processor and (3) the communication model.  Others rely to the parallel application such as: (1) the computation time and (2) the communication time of the application. 


This work of this thesis is focused on studying the iterative parallel  applications, where different parallel architectures
are used to execute them in parallel, while optimizing their energy consumptions.   
In this context, this chapter gives a brief overview about parallel hardware architectures and  parallel iterative applications. Also, it discusses an energy model proposed by other authors used to measure the energy consumption of these applications. 
The reminder of this chapter is organized as follows: section \ref{ch1:2} describes different types of  parallelism and different types of  parallel platforms. It also explains some models of parallel programming.  Section \ref{ch1:3} discusses both types of parallel iterative methods, synchronous and asynchronous ones and comparing them. Section \ref{ch1:4}, presents a well accepted energy model from the state of the art that can be used to measure the energy consumption of parallel iterative applications when  the frequency of  processor is changed. Finally, section \ref{ch1:5} summarizes this chapter.


\section{Parallel Computing  Architectures} 
\label{ch1:2}
The process of executing the calculations simultaneously over many computing units is called  parallel computing.
Its main principle refers to the ability of dividing a large problem into  smaller sub-problems that can be solved at the same time \cite{ref2}. 
Solving the sub-problems of one main problem in  parallel  is carried out in parallel  on multiple  processors.
Indeed, a parallel  architecture can be defined as a computing system that is composed of many processing elements, which are connected via a network model and some tools that are used to make the processing units work together  \cite{ref1}.
In other words, the parallel computing architecture consists of  software and hardware resources. 
Hardware resources are: (1) the processing units, (2) the memory model and (3) the network system that connects them. Software resources include (1) the specific operating system, (2) the programming language and (3) the compile or the runtime libraries. Besides,  parallel computing may have different levels of parallelism that can be performed in a software or a hardware level. Five types of parallelism levels have been defined as follows:
\begin{itemize}

\item \textbf{Bit-level parallelism (BLP)}: The appearance of  very-large-scale integration (VLSI) in 1970s has been viewed as the first step towards  parallel computing. It is used to increase the number of bits  in the word size which is processed by a processor as illustrated in the figure~\ref{fig:ch1:1}. For many successive years, the number of bits have been increased starting from 4 bit to 64 bit microprocessors. For example nowadays, the recent x86-64 architecture is the most common architecture. For a given application, the biggest the word size is the lesser  instructions to be executed by the processor.
 
\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/bits-para.pdf}
\caption{Bit-level parallelism }
\label{fig:ch1:1}
\end{figure}

\item \textbf{Data-level parallelism (DLP)}: Data parallelism is the process of distributing  data vector between  processors, where each one performs the same operations on its data sub-vector. Therefore, many arithmetic operations can be performed on the same data vector in a simultaneous manner. This type of parallelism can be used in many programs, especially in the area of scientific computing. Usually, data-parallel operations are only provided to arrays operations, for example, as shown in figure \ref{fig:ch1:2}.  Vector multiplication, image and signal processing can be considered as an example of applications that use this type of parallelism. 

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/data-para.pdf}
\caption{Data-level parallelism }
\label{fig:ch1:2}
\end{figure}


\item \textbf{Instruction-level parallelism (ILP)}: Generally, a sequential program is composed of many instructions. These instructions can be executed in  parallel at the same time, if each one of them is independent from the others. In particular, the parallelism can be achieved in  instruction level by using a pipeline. It means the input and output times of each instruction is overlapped by computations from other instructions. For example, if we have two instructions: $I_1$ and $I_2$, they are independent if there is no control and no data dependency between them.
In pipeline stages, the execution of each instruction is divided into multiple steps. Then, they can be overlapped with the steps of other instructions by a pipeline hardware unit.
Figure~\ref{fig:ch1:3} demonstrates four instructions, where each one has four steps denoted as: (1) fetch, (2) decode, (3) execute and  (4) write. Thus, they are implemented in hardware units by pipeline. 

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/pipelines.pdf}
\caption{Instruction-level parallelism by pipelines}
\label{fig:ch1:3}
\end{figure}



\item \textbf{Thread-level parallelism (TLP)}: It is also known as  task-level parallelism.
According to  Moore’s law \cite{ref9}, the number of transistors in a processor doubles each two years to increase its performance. Cache and main memory sizes  must also be increased in order to avoid data bottlenecks.
However,  increasing the number of transistors may generate some issues: (1) the first issue is related to drastically  increase in  cache size, which leads to a large access time. (2) the second issue is related to the huge increase in the number of the transistors per CPU, which  can increase significantly the heat dissipation.
Thus, CPUs constructors couldn't increase the frequency of the processor anymore due to these reasons. Therefore, they created multi-core processors. With multi-core processors, programmers subdivide their programs into multiple tasks which can be then executed in parallel over them to improve the performance, see figure~\ref{fig:ch1:4}. Each processor can have individual threads or multiple threads dedicated to each task. A thread can be defined as a part of the parallel program that shares processor resources with other threads. 

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/thread-para.pdf}
\caption{Thread-level parallelism}
\label{fig:ch1:4}
\end{figure}

Therefore, the execution time of a sequential program that is composed of $N$ tasks, is the sum of the execution times of all tasks. Thus, it is expressed as  follows:

\begin{equation}
\label{ch1:eq1}
    Sequential~execution~time = \sum_{i=1}^{N} T_i
\end{equation}

Whereas, if tasks are executed synchronously over multiple processing units in parallel, the execution time of the program is defined as the execution time of the task that has maximum the execution time (the slowest task) as follows:

\begin{equation}
\label{ch1:eq2}
    Parallel~execution~time = \max_{i=1,\dots,N} T_i
\end{equation}

\item \textbf{Loop-level parallelism (LLP)}:
Many  algorithms  execute iteratively the same program portion,  computations, many times using different forms of loop statements. At each iteration, the program needs to scan a large data structure such as  an array structure to perform the arithmetic calculations. Inside the loop structure, there are many instructions that are  dependent or independent. In a sequential loop execution,  the $i$ iteration must be executed after the completion of the $(i-1)$ iteration. 
If each iteration is independent from the others, then  all  iterations' instructions can be distributed over many  processors to be executed in  parallel,  
for example, see figure\ref{fig:ch1:5}. In the parallel programming languages, this type of loop is  called the  $parallel~loop$.

\begin{figure}[h!]
\centering
\includegraphics[scale=0.85]{fig/ch1/loop-para.pdf}
\caption{Loop-level parallelism}
\label{fig:ch1:5}
\end{figure}

The execution time of the parallel loop portion can be computed as 
the execution time of a sequential loop portion has $N_{iter}$ iterations divided by the number of the processing units $N_{processors}$ as follows:

\begin{equation}
\label{ch1:eq3}
 Parallel~loop~time = \frac{Sequential~loop~time}{N_{processors}}
                  =\frac{\sum_{i=1}^{N_{iter}} Time~of~iter_i}               
                   {N_{processors}}
\end{equation}

For more details about the levels of parallelism see \cite{ref3,ref4,ref6,ref7}.
\end{itemize}

\subsection{Types of Parallel platforms} 
\label{ch1:2:1}
The main goal behind using a parallel architecture is to solve a big problem faster.
A collection of processing elements must  work together to compute the final solution of the main problem. Many different architectures have been proposed  
and classified according to  parallelism in  instruction and data
streams. In 1966, Michel Flynn has proposed a simple model to categorize all computers  models that is still useful until now \cite{ref10}. His taxonomy is based on considering the data and the operations performed on this data to classify the computing systems into four types as follows:

\begin{itemize}
 
\item \textbf{Single instruction, single data (SISD) stream}: A single processor that executes a single instruction stream (i.e executing one data stream stored in an individual memory model, see figure \ref{fig:ch1:6}). 
The conventional sequential computer, according to Von Neumann model \cite{ref50}, also called the Uniprocessors can be viewed as an example of this type of architecture.
\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/sisd.pdf}
\caption{SISD machine architecture}
\label{fig:ch1:6}
\end{figure}
 
\item \textbf{Single instruction, multiple data (SIMD) stream}: All  processors execute the same instructions on different data. 
Each processor stores the data in its local memory. Then, they communicate with each others typically via a simple communication model, see figure \ref{fig:ch1:7}. Many scientific and engineering
applications are referred to this type of parallel scheme.
Vector and array processors are well known  examples of this type. 
Examples about the applications executed over this architecture: (1) graphics processing, (2) video compression and (3) medical image analysis applications.

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/simd.pdf}
\caption{SIMD machine architecture}
\label{fig:ch1:7}
\end{figure}

\item \textbf{Multiple instruction, single data (MISD) stream}: Many operations from multiple processing elements are executed over the same data stream. Each processing element has its local memory to store the private program instructions. Then, these instructions are applied to unique global memory data stream as in figure \ref{fig:ch1:8}. While the MISD machine is not commonly used,  there are some interesting uses such as the systolic arrays and dataflow machines.

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/misd.pdf}
\caption{MISD machine architecture}
\label{fig:ch1:8}
\end{figure}


\item \textbf{Multiple instruction, Multiple data (MIMD) stream}: There are multiple processing elements, each one has a separate instruction  and  local data memories.
At any time, different processing elements may be used to execute different instructions on  different data fragment, see figure \ref{fig:ch1:9}. There are two types of MIMD machines: the shared memory and the message passing MIMD machines. 
In the former, processors  communicate via a shared memory model, while in the latter, each processor has its own local memory and all processors communicate with each others via a communication network model. The  multi-core processors, local clusters and grid systems are  some examples for  MIMD machine.
Many applications have been developed based on this architecture 
such as computer-aided design, computer-aided manufacturing, simulation, modeling, iterative applications and so on.

 \begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/mimd.pdf}
\caption{MIMD machine architecture}
\label{fig:ch1:9}
\end{figure}
\end{itemize}
 For more details about this architectural taxonomy see \cite{ref11,ref5,ref13,ref14}.

The work of this thesis is dedicated to MIMD machine's architecture. Therefore, we discuss in
this chapter some of the commonly used parallel architectures that belong to MIMD machines.
As explained before,  MIMD architectures can be classified into two types, the shared memory and the distributed message passing ones. Furthermore, these classifications are based on 
how MIMD processors access the memory model. The shared MIMD machine communication topology can be bus-based, extended or hierarchical type. Whereas, the distributed memory MIMD machine may have hypercube or mesh interconnected networks. In the following  some well known MIMD parallel computing platforms are explained:

\begin{itemize}
\item \textbf{Multi-core processors}:
The multi-core processor is a single chip component with two or more processing units. These processing units are called cores, which are connected to each other via a main memory model as in the figure \ref{fig:ch1:10}. Each individual core has its own cache memory to store  data. Moreover, each core may have  one or more threads to execute a specific programming task as shown in the thread-level parallelism. Historically, the multi-cores of the CPU began as two-core processors, then the number of cores  doubled with each semiconductor process generation \cite{ref12}. The graphic processing units (GPU) use extensively the multi-core architecture, 
the NVIDIA  GeForce TITAN Z has 5700 cores in the year of 2015 \cite{ref17}. While, in the same year a general-purpose microprocessor (CPU) has a lot less cores, for example the TILE-MX processor from Tilera has 100 cores  \cite{ref16}. For more details about the multi-core processors see \cite{ref15}.

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/multicores.pdf}
\caption{Multi-core processor architecture}
\label{fig:ch1:10}
\end{figure}


\item \textbf{Local Cluster}:
 is a collection of independent  computers that are connected
to each other  via  a high speed  
local area network (LAN) with low latency and big bandwidth. Moreover, each node communicates with other nodes  using messages. All the nodes in the cluster must be controlled by one node called the master node, which is a specific node used to handle the scheduling and the management of the other nodes as shown in the figure \ref{fig:ch1:11}. Usually, all the nodes are homogeneous, they have the same specifications in term of  computing power and memory.  Also, all the computing nodes in the cluster run the same  operating system. See \cite{ref18, ref19} for more information about the cluster and its applications.

\begin{figure}[h!]
\centering
\includegraphics[scale=1]{fig/ch1/cluster.pdf}
\caption{Local cluster architecture}
\label{fig:ch1:11}
\end{figure}


\item \textbf{Grid (Distributed clusters)}:
Grid is a collection of  computing clusters from different sites that are connected via a wide area network (WAN). 
In particular, different local clusters compose the grid are geographically located far away from each others. Usually, each  cluster is composed of homogeneous nodes, which are different from  nodes of the other clusters located in different sites. These nodes can be different in their hardware and software specifications (i.e their computing power, their memory size, their operating system and their network: latency and bandwidth). Figure \ref{fig:ch1:12} presents an example of a grid that is composed of three heterogeneous clusters that are located in  different sites and  connected via a wide area network.  Furthermore, the grid can  refer to an infrastructure  that applies the integration and the collaboration by using  a collection  of different computers, networks, database servers  and scientific devices, which  belong to  many companies and universities. Therefore, wide heterogeneous computing resources are available to be used simultaneously by different users. Note that, the main bottleneck of the grid is the high latency communications between the nodes from different sites. 
See \cite{ref20} for more information about the grid and its applications.

\begin{figure}[h!]
\centering
\includegraphics[scale=0.85]{fig/ch1/grid.pdf}
\caption{Grid architecture}
\label{fig:ch1:12}
\end{figure}

\end{itemize}


\subsection{Parallel programming Models} 
\label{ch1:2:2}
Many parallel programming languages and libraries  have been developed 
to explore the computing power of the parallel architectures. In this section,
two types of parallel programming languages are investigated: (1) shared and (2) distributed programming models. Moreover, each  type is divided  into two subcategories according to their supporting level for the number of computing units from which  the parallel platform is composed.
Figure \ref{fig:ch1:14} presents this classification hierarchy of the parallel programming 
models. 

\begin{figure}[h!]
\centering
\includegraphics[scale=0.75]{fig/ch1/classification.pdf}
\caption{The classification of the parallel Programming Models}
\label{fig:ch1:14}
\end{figure}


Many programming interfaces and libraries have been developed to compile and run the 
parallel applications over the parallel architectures. In the following, 
some examples for each type of the parallel programming models are discussed:

\begin{itemize}
\item \textbf{Local cluster programming models}
  \begin{itemize}
    \item \textbf{MPI} \cite{ref23} is the Message Passing Interface and it is considered as a 
                      standardization 
                      dedicated to message passing in a distributed memory environment.
                      The first version of MPI was designed by a group of researchers in
                      1991. It  is a specification and have been implemented in many programming 
                      languages such as C, Fortran and 
                      Java.   
                      The MPI functions are not only limited to  point to point operations for 
                      sending and receiving messages, there are many others collective 
                      operations such as gathering and reduction operations. 
                      While MPI is not designed for grid,
                      it  is widely used as the communication interface for grid  applications 
                      \cite{ref52}. 
                    In this work,   MPI was used  in programming  our algorithms and applications which are
                    implemented in both Fortran and C programming languages.  
                      
                 
  \end{itemize} 
  

 
\item \textbf{Multi-core CPU programming models} 
  \begin{itemize}
   \item \textbf{OpenMP}  \cite{ref34} is a  parallel programming tool dedicated to shared memory 
                architectures. The main goal of using this programming model is to provide 
                a standard and portable API (application programming interface) to  write
                shared memory parallel programs. It can be used with many  programming languages such 
                as C, C++ and Fortran in order to support different types of shared memory platforms 
                such as multi-core processors.
                OpenMP uses multi-threading, which is a model in parallel programming 
                that uses a master thread to control a set of slave threads. Each
                thread can be executed in parallel by assigning it to a processor.  
                Moreover, OpenMP can be  used with MPI to support hybrid platforms which have 
                shared and distributed memory models at the same time.
                
  
    \end{itemize}

  
\item \textbf{GPU programming models} 
  \begin{itemize}
   \item \textbf{CUDA} \cite{ref37} Modern graphical processing units (GPUs) have increased its chip-level  
                       parallelism.  Current  NVIDIA  GPUs  consist of many-cores processors that have 
                       thousands of cores. To make their GPUs a general purpose computing processor in 2007 
                       the NVIDIA has  developed CUDA a parallel programming  language.
                       A CUDA program has two parts: host and kernels.  The host  code is  sequentially 
                       executed over the CPU. 
                       While, the kernels are executed in parallel over the GPUs.
 
   \item \textbf{OpenCL}\cite{ref38} is for Open Computing Language. It is a parallel 
                       programming language dedicated for heterogeneous platforms composed 
                       of CPUs and GPUs. The first release of this language has initially been developed 
                       by Apple in 2008. Functions that are executed over OpenCL devices are called kernels. 
                       They are portable and can be executed on any computing hardware such as CPU or GPU
                       cores. 
                     
                         
                                   
  \end{itemize}
  
 
\end{itemize}


\section{Iterative Methods} 
\label{ch1:3}
In this work, we are interested in solving system of linear equations which are very common in the scientific field. A system of linear equations can be expressed as follows:


\begin{equation}
  \label{eq:linear}
 A x = b
\end{equation}

Where $A$ is a two dimensional matrix of size $N \times N$, $x$ is the unknown vector,
and $b$ is a vector of constant, each of size $N$. There are two types of solution methods to solve this linear system: the \textbf{direct} and the \textbf{iterative methods}.
A direct method executes a finite number of steps, depending on the 
size  of the linear system and gives the exact solution of the system. If the problem  is very big, this method is expensive or its
solution is impossible in some cases.  On the other hand, methods with iterations execute the same block of instructions many times. The number of iterations can be predefined or the application iterates until a criterion is satisfied. Iterative methods are methods with iterations that start from an initial guess and 
improve successively the solution until reaching an acceptable approximation of the exact solution. 
These methods are well adapted for large systems and can be easily parallelized. 

A sequential iterative algorithm is typically organized as a series of steps essentially  of the form:

\begin{equation}
  \label{eq:iter}
   X^{(k+1)} \longleftarrow F(X^k) 
\end{equation}

Where $F$ is one or set of operations applied to the data vector $X^k$ to produce the new data vector $X^{(k+1)}$. The operation $F$ is applied sequentially many times until satisfying the convergence condition as in the   algorithm \ref{sia}.



\begin{algorithm}[h!]
\begin{algorithmic}[1]
  
    \State Initialize the vector $X^0$ randomly  
    \For {$k:=1$  to \textit{convergence}}
    
      \State $X^{(k+1)} = F(X^k)$ 
   \EndFor
   \end{algorithmic}
   \caption{The iterative sequential algorithm}
  \label{sia}
   
\end{algorithm}

The sequential iterative algorithm at each iteration computes the value of the relative error, which is called the residual and denoted as $R$. This error value can be computed as the maximum difference  between the  data components of the vectors of the last two successive iterations as follows:

 \begin{equation}
  \label{eq:res}
   R = \max_{i=1, \dots, N}  \abs{X_i^{(k+1)} - X_i^k}
\end{equation}  
Where $N$ is the size of the vector $X$. Then, the iterative sequential algorithm stops  iterating if the maximum error between the last two successive solution vectors, as in \ref{eq:res}, is less than or equal to a threshold value. Otherwise, it replaces the new vector $X^{(k+1)}$ with the old vector $X^k$ and computes a new iteration.


\subsection{Synchronous Parallel Iterative method} 
\label{ch1:3:1}
The sequential iterative algorithm \ref{sia} can be parallelized by executing it on many computing units. To solve this algorithm on $M$ computing units, first the elements of the problem vector $X$ must be subdivided into $M$ sub-vectors, $X^k=(X_1^k,\dots,X_M^k)$. 
Each sub-vector can be solved  independently on one computing unit as follows:

\begin{equation}
  \label{eq:subvector}
   X_i^{k+1}= F_i(X_1^k,\dots,X_M^k)  \hspace{1cm} where \hspace{0.2cm} i=1,\dots, M
\end{equation}

Where $X_i^k$ is the sub-vector executed over the $i^{th}$ computing unit at the iteration $k$.

\begin{algorithm}[h!]
\begin{algorithmic}[1]
  
  \State Initialize the sub-vectors $(X_1^0,\dots,X_M^0)$   
    \For {$k:=1$  step $1$ to \textit{convergence}}
       \ParFor {$i:=1$   to \textit{M}}
        \State $X^{(k+1)} = F(X^k)$
      \EndParFor
    \EndFor  

   
   \end{algorithmic}
   \caption{The synchronous parallel iterative algorithm}
  \label{spia}
\end{algorithm}


The algorithm \ref{spia} represents the synchronous parallel iterative algorithm. Similarly to 
the sequential iterative algorithm \ref{spia}, this algorithm stops iterating when the convergence condition  is satisfied.
We consider that the keyword \textbf{parfor} is used to make a for loop in parallel.

This algorithm needs to satisfy a convergence condition which  is called the  global convergence condition. In order to detect the global convergence overall computing units, first we need to compute
at each iteration the local residual. Then at the end of each iteration, all the local residuals  from $M$ computing units must be reduced to one maximum  value represented by the  global residual.
For example, in MPI this operation is directly applied using a high level communication procedure  called \textit{AllReduce}. The goal of this communication procedure is to apply the reduction operation on all local residuals computed by the computing units.


\begin{figure}[h!]
\centering
\includegraphics[scale=0.75]{fig/ch1/sisc.pdf}
\caption{The SISC Model}
\label{fig:ch1:15}
\end{figure}


In a synchronous parallel iterative algorithm, computing processors need to communicate with each others to 
exchange data at each iteration if there is a dependency between the parallel tasks. Algorithm \ref{spia}  use synchronous iterations and synchronous communications  denoted as \textbf{SISC} model.  At each iteration, the computing processor waits until 
it  receives all the  computed data at the previous iteration from other processors to perform the next iteration. Figure \ref{fig:ch1:15}, shows that using SISC model in a heterogeneous platform may result in  big periods  of the idle times represented by the white dashed spaces between two successive iterations. Indeed, this happens when the fast computing processors wait for the slower ones to finish their iterations to be able to synchronously send their data to them. 
Using this operation, faster processors waste a big amount of their computing power and thus consume uselessly energy.
The increase in the heterogeneity in the computing powers between the  processors may increase proportionally these idle times.
Accordingly, this algorithm can be  effectively run over a local cluster, where a high speed local network is used to reduce these idle times.  


\begin{figure}[h!]
\centering
\includegraphics[scale=0.75]{fig/ch1/siac.pdf}
\caption{The SIAC Model}
\label{fig:ch1:16}
\end{figure}

Furthermore, the communications of the synchronous iterative algorithm can be replaced by asynchronous ones. The resulting algorithm is called  Synchronous Iterations with Asynchronous 
Communications  and denoted as \textbf{SIAC} algorithm. The main principle of this algorithm is to use  synchronize iterations while exchanging the data between the computing units asynchronously.
Moreover, each computing unit does not need to wait for its neighbours to receive the data messages 
that it has sent, while it only waits to receive  data from them. This can be implemented with SISC algorithm that is programmed in MPI by replacing the synchronous send of the messages by asynchronous ones, while keeping  
the synchronous receive. The only advantage of this technique is to reduce the idle times between iterations by allowing the communications to overlap partially
with computations, see figure \ref{fig:ch1:16}. The idle times are not totally eliminated  because the
fast computing nodes must  wait for slow ones to send their data messages. 
SISC and SIAC algorithms are not tolerant to the loss of data messages. Consequently, if one node crashes, all the other computing nodes are blocked.


 
\subsection{Asynchronous Parallel Iterative method} 
\label{ch1:3:2}
The asynchronous iterations mean that all processors perform their iterations without considering the works of  other processors. Each processor does not have to wait to receive 
data messages from  other processors and continues to compute the next iteration using the last data received from neighbours. Therefore, there  are no  idle times at all between the iterations as in Figure \ref{fig:ch1:17}.  This figure indicates that  fast processors can perform more iterations than  the slower ones at the same time. 
The asynchronous iterative algorithm that uses an asynchronous communications  is called  \textbf{AIAC} algorithm. Similarly to the SISC algorithm, the AIAC algorithm subdivides the global vectors $X$ into $M$ sub-vectors between the computing units. The main difference between the two algorithms is that these $M$ sub-vectors are not updated at each iteration in the AIAC algorithm because both  iterations and communications are asynchronous. 


\begin{figure}[h!]
\centering
\includegraphics[scale=0.75]{fig/ch1/aiac.pdf}
\caption{The AIAC Model}
\label{fig:ch1:17}
\end{figure}

The global convergence detection of the asynchronous parallel iterative is not trivial.
For more information about the convergence detection techniques of the asynchronous iterative methods, refer to \cite{ref40,ref41,ref42,ref43} for more details. 


The implementation of the AIAC method is not easy, but it gives many advantages over the traditional synchronous iterative method:

\begin{itemize}
\item It prevents the existence of idle times, since each processor does not have to wait 
      to receive the data messages from its neighbours to compute the next iteration.
      
\item Less sensitive for the heterogeneous communications and nodes' computing powers. In heterogeneous 
      platform, the fast nodes do not need to wait for the slow ones, and they can  perform more iterations
      compared to them. While in the traditional synchronous iterative methods, the fast computing nodes perform
      the same number of iterations as the slow ones because they are blocked. 

\item The loss of data messages is totally tolerant because each computing unit is not  
      blocked waiting for the message. If the message is lost, the destination node does not have to wait  
      for this data message and it uses the last received data to perform its iteration  
      independently.
      
\item In the grid architecture, the local clusters from different sites are 
      connected via a slow network with a high latency. The use of the AIAC model 
      reduces the delay of sending the data message over such slow network link and thus the performance 
      of the applications is not affected.
\end{itemize}


In addition to the difficulty of applying the asynchronous iterative model, it has some 
disadvantages that can be summarized by these points:

\begin{itemize}
\item It is not compatible with all types of the iterative applications because some of these 
      applications need to receive  data messages  at each iteration or they would not converge. 
 
\item An asynchronous iterative method requires more iterations compared 
      to the synchronous one to converge. The increase in the number of iterations may increase proportionally 
      the execution time of the application if it is being executed on a fast homogeneous cluster.
    
\item Since each node does not receive  new data messages at each iteration,  detecting the global convergence 
      is harder than for the synchronous model. 
      Therefore, in AIAC algorithm a process can perform many iterations    
      without receiving any data messages from its neighbours. The absence of receiving new 
      data messages makes the data component invariant at the computing units and thus it provides 
      a false local convergence.  At the reception of the first data message,
       the local subsystem will  diverge after computing the next iteration. 
      Therefore, special mechanisms are required for detecting the global convergence of a parallel 
      iterative algorithm implemented according to the asynchronous iteration model.


\end{itemize}


In work of this thesis, we are interested in optimizing the energy consumption of parallel iterative 
methods running over clusters or grids. 



\section{The energy consumption model of a parallel application} 
\label{ch1:4}

Many researchers~\cite{ref46,ref47,ref48,ref49} divide the power consumed by a processor into
two power metrics:  static power and  dynamic power.  The first one is
consumed as long as the computing unit is on, the latter is only consumed during
computation times.  The dynamic power $P_{dyn}$ is related to the switching
activity $\alpha$, load capacitance $C_L$, the supply voltage $V$ and
operational frequency $F$, as shown in EQ~(\ref{eq:pd}).
\begin{equation}
  \label{eq:pd}
  P_\textit{dyn} = \alpha \cdot C_L \cdot V^2 \cdot F
\end{equation}
The static power $P_{static}$ captures the leakage power as follows:
\begin{equation}
  \label{eq:ps}
   P_\textit{static}  = V \cdot N_{trans} \cdot K_{design} \cdot I_{leak}
\end{equation}
Where V is the supply voltage, $N_{trans}$ is the number of transistors,
$K_{design}$ is a design dependent parameter and $I_{leak}$ is a
technology-dependent parameter.  


The dynamic voltage and frequency scaling technique (\textbf{DVFS}) is a process that is allowed in modern processors to reduce the dynamic
power by scaling down the voltage and frequency of the CPU.  Its main objective is to
reduce the overall energy consumption of the CPU~\cite{ref77}.  The operational frequency $F$
depends linearly on the supply voltage $V$ as follows:
\begin{equation} 
\label{eq:v}
V = \beta \cdot F
\end{equation}

 Where $\beta$ is some of constant.  This equation is used to study the change of the dynamic
voltage with respect to various frequency values in~\cite{ref47}.  The reduction
process of the frequency can be expressed by the scaling factor $S$ which is the
ratio between the maximum and the new frequency as in EQ~(\ref{eq:s}).
\begin{equation}
  \label{eq:s}
 S = \frac{F_\textit{max}}{F_\textit{new}}
\end{equation}
The value of the scaling factor $S$ is greater than 1 when changing the
frequency of the CPU to any new frequency value~(\emph{P-state}) in the
governor.  The CPU governor is an interface driver supplied by the operating
system's kernel to lower a core's frequency \cite{ref8}.  

Depending on the equation \ref{eq:s}, the new frequency $F_{new}$ can be calculated as follows:

\begin{equation}
  \label{eq:fnew}
  F_\textit{new}= S^{-1} \cdot  F_\textit{max}
\end{equation}


Replacing $V$  in \ref{eq:pd} as in \ref{eq:v} gives the following equation of the dynamic power consumption
as a function of the constant $\beta$ instead of $V$: 

\begin{equation}
  \label{eq:pd-beta}
   P_{dyn}= \alpha \cdot C_L \cdot (\beta \cdot F) ^2 \cdot  F  =\alpha \cdot C_L \cdot \beta^2 \cdot  F^3
\end{equation}

Replacing $F_{new}$ in \ref{eq:pd-beta} as in \ref{eq:fnew} gives the following equation for dynamic power consumption:

\begin{multline}
  \label{eq:pdnew}
   P_{dynNew} = \alpha \cdot C_L \cdot \beta^2 \cdot  F_{new}^3 = 
   \alpha \cdot C_L \cdot \beta^2 \cdot  F_{max}^3 \cdot S^{-3} =
   \alpha \cdot C_L \cdot (\beta \cdot  F_{max})^2 \cdot F_{max} \cdot S^{-3} \\
   {} =\alpha \cdot C_L \cdot V^2 \cdot F_{max} \cdot S^{-3} = P_{dyn} \cdot S^{-3}
\end{multline}

Where $P_{dynNew}$  and $P_{dyn}$ are the  dynamic powers consumed with the
new frequency and the maximum frequency respectively.

According to (\ref{eq:pdnew}) the dynamic power is reduced by a factor of
$S^{-3}$ when reducing the frequency of a processor by a factor of $S$.
The energy consumption is measured in Joule, and can be calculated by
multiplying the power consumption, measured in watts, by the  execution time of the program as follows:

\begin{equation}
  \label{eq:E}
  Energy = Power \cdot T
\end{equation}

According to the equation \ref{eq:E}, the dynamic energy consumption of the program executed in the time $T$ over one processor is the dynamic power multiplied by the execution time. Moreover, the frequency scaling factor $S$ increases the execution time of the processor linearly, then the new dynamic energy consumption can be computed as follows:

\begin{equation}
  \label{eq:Edyn}
   E_{dynNew} = P_{dyn} \cdot S^{-3} \cdot (T \cdot S)= S^{-2} \cdot P_{dyn} \cdot  T
\end{equation}


According to \cite{ref46,ref47}, the static power consumption $P_{static}$  does not changed when the frequency of the processor is scaled down. Therefore, the static energy consumption can be computed as follows:
\begin{equation}
  \label{eq:Estatic}
   E_{static} = S \cdot  P_{static}  \cdot T
\end{equation}


Therefore, the energy consumption of an individual task running over one processor 
is the sum of both static and dynamic energies that  can be computed as follows:
\begin{equation}
 \label{eq:Eind}
  E_{ind} =  E_{dynNew} + E_{static} = S^{-2} \cdot P_{dyn} \cdot  T + S \cdot  P_{static}  \cdot T
\end{equation}

 
The total energy consumption of $N$  parallel task  running on $N$ processors is the summation  of the individual energies consumed by all processors. This model is developed and used by  Rauber and Rünger~\cite{ref47}. 
The total energy consumed by the parallel tasks running on a homogeneous platform is computed by sorting the execution time of the all parallel tasks in a descending order, then using EQ~(\ref{eq:energy}).

\begin{equation}
  \label{eq:energy}
  E_\textit{~all~tasks} = P_\textit{dyn} \cdot S_1^{-2} \cdot
    \left( T_1 + \sum_{i=2}^{N} \frac{T_i^3}{T_1^2} \right) +
    P_\textit{static} \cdot T_1 \cdot S_1 \cdot N
 \hfill
\end{equation}

Where $N$ is the number of parallel tasks, $T_i$  for $i=1,\dots,N$ are
the execution times of the sorted tasks.  Therefore, $T1$ is
the time of the slowest task, and $S_1$ its scaling factor which should be the
highest because they are proportional to the time values $T_i$. 
Finally, model \ref{eq:energy}  can be used to measure the energy consumed by any parallel application such as the iterative parallel applications with respect to the new scaled frequency value. 

There are two drawbacks in this energy model as follows:
\begin{itemize}
\item The message passing iterative program consists of  communication and computation times.
      This energy model assumes that the dynamic power is consumed during both these times.
      While the processor during the communication times remains idle and only consumes the static 
      power, for more details see \cite{ref53}. 


\item It is not well adapted to a heterogeneous architecture when there are different 
      types of  processors, which  consume different dynamic and static powers. 
\end{itemize}

Therefore, one of the more important goals of this work is to develop a new energy models that 
 take into consideration the communication times in addition to the  computation times in order to modelize and measure the energy consumptions of the parallel iterative methods. These models must be suitable to  homogeneous or heterogeneous parallel architectures.  

\section{Conclusion}
\label{ch1:5}
In this chapter, three sections have been presented to describe the parallel hardware architectures, the parallel iterative applications and the energy consumption model used to measure the energy consumption of these applications. 
The different types of parallelism levels that can be implemented in  software and hardware techniques have been explained in the first section. Afterwards,  different types of  parallel architectures have been discussed and classified according to the connection between the computation units and the memory model.  
Both  shared and distributed platforms as well as their depending parallel programming models have been categorized.
In the second section, the two types of parallel iterative methods: synchronous and asynchronous ones were presented. The synchronous iterative methods are well adapted to local homogeneous clusters with a high speed network link, while the asynchronous iterative methods are more suited to the distributed heterogeneous clusters. 
Finally, in the third section, an energy consumption model proposed in the state of the art to  measure the energy consumption of parallel applications was explained. This model  cannot be used for all types of parallel architectures. Since, it assumes  that the dynamic power is consumed during both of the communication and computation times, while the processor involved remains idle during the communication times and  only consumes the static power. Moreover, it is not well adapted to  heterogeneous architectures when there are different types of processors, that consume different dynamic and static powers.

For these reasons, in the next chapters of this thesis  new energy consumption models are developed to efficiently predict the energy consumed by parallel iterative methods running on both homogeneous and heterogeneous architectures.  Additionally, these energy models are used in a method  that optimizes  both  energy consumption and performance of an iterative message passing application.