11 project : $(PROJECT).prj
13 compile : $(PROJECT).prj $(VHDL_SRC)
14 tb_name=$$( echo $(TB_SRC) | sed 's,.*/,,' | sed 's,[.].*,,'); \
15 fuse $(ISIM_LIB).$$tb_name $(ISIM_LIB).glbl -prj $(PROJECT).prj -L unisim -L secureip -timeprecision_vhdl ps -o $(SIMU_EXE)
18 $(SIMU_EXE) -gui -wdb $(SIMU_EXE).wdb
21 if [ -f $@ ]; then rm $@; fi
22 echo "### VHDL sources"
23 for fich in $(VHDL_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done
24 echo "### verilog sources"
25 for fich in $(VL_SRC); do echo verilog $(ISIM_LIB) $$fich >> $@; done
26 echo "### test bench sources"
27 for fich in $(TB_SRC); do echo vhdl $(ISIM_LIB) $$fich >> $@; done
32 cd $(SRC_DIR); rm -f *~
33 cd $(TB_DIR); rm -f *~