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finished VHDL gen. (but have to test further
[blast.git] / lib / sources / tools_pkg.vhd
1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4
5 package tools_pkg is
6   type vector_of_std_logic_vector18 is array (natural range <>) of std_logic_vector(17 downto 0);
7   type vector_of_std_logic_vector8 is array (natural range <>) of std_logic_vector(7 downto 0);
8   type vector_of_std_logic is array (natural range <>) of std_logic;
9   type vector_of_unsigned8 is array (natural range <>) of unsigned(7 downto 0);
10   type vector_of_std_logic_vector4 is array (natural range <>) of std_logic_vector(3 downto 0);
11 end tools_pkg;