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finished VHDL gen. (but have to test further
[blast.git] / source-2O.xml
1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
2 <block>
3   <informations>
4     <name>
5       source-2O
6     </name>
7     <category ids="6" />  
8     <description>
9       <brief>
10         A testing source block, with 2 outputs
11       </brief>
12       <detailed>
13         A testing source block, with 2 outputs  
14       </detailed>     
15     </description>    
16   </informations>
17
18   <parameters>
19     <parameter name="data_width" type="string" value="8" context="user"/>
20   </parameters>
21
22   <interfaces>
23     <inputs>
24       <input name="clk" width="1" purpose="clock" />
25       <input name="rst" width="1" purpose="reset" />
26     </inputs>
27     <outputs>
28       <output name="data1_o" width="$data_width"/>
29       <output name="data2_o" width="$data_width"/>      
30     </outputs>
31   </interfaces>
32
33 </block>