1 <!DOCTYPE rgb3sx8_to_gs>
2 <block_impl ref_name="rgb3sx8_to_gs.xml" ref_md5="">
4 <author lastname="" mail="" firstname=""/>
5 <log creation="2018-05-02">
12 <package name="std_logic_1164" use="all"/>
13 <package name="numeric_std" use="all"/>
18 signal do_mult : std_logic;
19 signal do_out : std_logic;
20 signal count : unsigned (2 downto 0);
21 signal accum : unsigned(dsp_in_width-1 downto 0);
22 signal result : unsigned(dsp_out_width-1 downto 0);
23 signal cst_mult : unsigned(dsp_in_width-1 downto 0); -- eq. 87382 to do /3
27 cst_mult <= to_unsigned(87382, 18);
29 accum_process : process (@{clk}, @{reset})
31 if @{reset} = '1' then
32 count <= to_unsigned(0, 3);
33 accum <= to_unsigned(0, dsp_in_width);
36 elsif rising_edge(@{clk}) then
40 if @{rgb_in_enb} = '1' then
43 accum <= resize(unsigned(@{rgb_in}), dsp_in_width);
44 count <= to_unsigned(1, 3);
46 accum <= accum + resize(unsigned(@{rgb_in}), dsp_in_width);
47 count <= to_unsigned(2, 3);
49 accum <= accum + resize(unsigned(@{rgb_in}), dsp_in_width);
50 count <= to_unsigned(0, 3);
56 end process accum_process;
58 mult_process : process (@{clk}, @{reset})
60 if @{reset} = '1' then
61 result <= to_unsigned(0, dsp_out_width);
63 elsif rising_edge(@{clk}) then
67 result <= accum * cst_mult;
71 end process mult_process;
73 @{gs_out} <= std_logic_vector(result(dsp_in_width+7 downto dsp_in_width));
74 @{gs_out_enb} <= do_out;
79 <input pattern="111" name="rgb_in_enb"/>
81 <production counter="3">
82 <output pattern="00001" name="gs_out_enb"/>