1 #include "GroupBlock.h"
2 #include "BlockParameterGeneric.h"
3 #include "AbstractInterface.h"
4 #include "ConnectedInterface.h"
5 #include "GroupInterface.h"
8 #include "Parameters.h"
10 int GroupBlock::counter = 1;
12 GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() {
14 GroupInterface* clk = NULL;
15 GroupInterface* rst = NULL;
17 // force topGroup to false if this group has a parent
18 if (_parent != NULL) {
20 name = QString("sub_group")+"_"+QString::number(counter++);
21 // creating clk/rst interfaces
22 clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
23 rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
29 name = QString("top_group");
30 // creating external clk/rst interfaces
31 clk = new GroupInterface(this,"ext_clk", AbstractInterface::Input, AbstractInterface::Clock);
32 rst = new GroupInterface(this,"ext_reset", AbstractInterface::Input, AbstractInterface::Reset);
35 // creating clkrstgen block and connecting it to this: done in Dispatcher since this has no access to library
39 if (_parent != NULL) {
44 AbstractBlock* source = (AbstractBlock *)(e.getSource());
45 cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
52 GroupBlock::~GroupBlock() {
53 foreach(AbstractBlock* block, blocks) {
58 bool GroupBlock::isGroupBlock() {
62 bool GroupBlock::isTopGroupBlock() {
66 void GroupBlock::setParent(AbstractBlock *_parent) {
73 void GroupBlock::removeAllBlocks() {
74 foreach(AbstractBlock* block, blocks) {
75 if (block->isGroupBlock()) {
76 GroupBlock* group = AB_TO_GRP(block);
77 group->removeAllBlocks();
83 void GroupBlock::removeBlock(AbstractBlock* block) {
84 /* CAUTION: no check is done if the block has connected interface
85 or not. Thus, they must be deleted elsewhere.
87 blocks.removeAll(block);
91 AbstractBlock *GroupBlock::getFunctionalBlockByName(QString name) {
92 foreach(AbstractBlock* block, blocks) {
93 if (block->isFunctionalBlock()) {
94 if (block->getName() == name) return block;
100 void GroupBlock::parametersValidation(QList<AbstractBlock *> *checkedBlocks, QList<AbstractBlock *> *blocksToConfigure) {
103 checkedBlocks->append(this);
105 foreach(BlockParameter* param, params){
106 if(param->isUserParameter() && !param->isValueSet()){
107 if(!blocksToConfigure->contains(param->getOwner())){
108 blocksToConfigure->append(param->getOwner());
112 foreach(AbstractInterface *inter, outputs){
113 foreach(AbstractInterface *connectedInter, inter->getConnectedTo()){
114 if(!checkedBlocks->contains(connectedInter->getOwner())){
115 connectedInter->getOwner()->parametersValidation(checkedBlocks, blocksToConfigure);
122 void GroupBlock::addGenericParameter(QString name, QString type, QString value) {
123 BlockParameter* param = new BlockParameterGeneric(this, name, type, value);
124 params.append(param);
127 void GroupBlock::removeGenericParameter(QString name) {
128 BlockParameter* p = getParameterFromName(name);
129 if (p != NULL) params.removeAll(p);
132 void GroupBlock::createInputPattern() {
133 foreach(AbstractInterface* iface, getControlInputs()) {
134 ConnectedInterface* connIface = AI_TO_CON(iface);
135 QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
136 connIface->setOutputPattern(pattern);
140 void GroupBlock::computeAdmittanceDelays() throw(Exception) {
141 throw(Exception(INVALID_GROUPBLOCK_USE));
144 void GroupBlock::checkInputPatternCompatibility() throw(Exception){
145 throw(Exception(INVALID_GROUPBLOCK_USE));
149 void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
151 static QString fctName = "GroupBlock::computeOutputPattern()";
153 cout << "call to " << qPrintable(fctName) << endl;
156 cout << "computing output pattern of group " << qPrintable(name) << endl;
158 bool canCompute = false;
159 // get the input pattern on each inputs
160 createInputPattern();
162 cout << "Input pattern OK" << endl;
163 // find blocks that are connected to that inputs and generators
164 QList<AbstractBlock*> fifo;
165 foreach(AbstractBlock* block, blocks) {
168 // if a block is a generator and has control outputs, add it
169 if (block->isGeneratorBlock()) {
170 if (block->getControlOutputs().size() > 0) addIt = true;
173 // if the block has all its connected control inputs that are connected to an intput of the group, add it too
174 if (block->getControlInputs().size() > 0) {
176 foreach(AbstractInterface* iface, block->getControlInputs()) {
177 //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
178 ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
179 //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
181 if (connFrom == NULL) {
185 else if (connFrom->getOwner() != this) {
193 cout << "adding " << qPrintable(block->getName()) << " to initialize the FIFO" << endl;
194 block->setTraversalLevel(0); // level 0 = first blocks to be evaluated
199 while (!fifo.isEmpty()) {
200 AbstractBlock* block = fifo.takeFirst();
202 if (block->getPatternComputed()) continue; // block has already been processed
204 cout << "computing compat and output for " << qPrintable(block->getName()) << endl;
208 block->checkInputPatternCompatibility();
211 cout << qPrintable(block->getName()) << " is not compatible with its input pattern" << endl;
216 block->computeOutputPattern();
219 cout << "cannot finalize output pattern computation of " << qPrintable(block->getName()) << endl;
223 block->setPatternComputed(true);
224 /* add other blocks connected from block to the fifo but only if
225 all their connected inputs are connected to blocks that have
228 foreach(AbstractInterface* iface, block->getControlOutputs()) {
229 ConnectedInterface* conn = (ConnectedInterface*)iface;
230 foreach(ConnectedInterface* connTo, conn->getConnectedTo()) {
232 AbstractBlock* block1 = connTo->getOwner();
233 cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl;
237 foreach(AbstractInterface* iface, block1->getControlInputs()) {
238 //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
239 ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
240 //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
242 if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) {
247 if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel();
252 cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl;
253 block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated
261 foreach(AbstractInterface* iface, getControlOutputs()) {
262 ConnectedInterface* connIface = AI_TO_CON(iface);
263 QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
264 connIface->setOutputPattern(pattern);
266 setPatternComputed(true);
270 void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
272 QString coreFile = "";
275 coreFile.append(Parameters::normalizeName(name));
276 coreFile.append(".vhd");
278 QFile vhdlCore(coreFile);
280 if (!vhdlCore.open(QIODevice::WriteOnly)) {
281 throw(Exception(VHDLFILE_NOACCESS));
284 cout << "generate VHDL of block " << qPrintable(name) << " in " << qPrintable(coreFile) << endl;
285 QTextStream outCore(&vhdlCore);
287 QDomElement dummyElt;
289 generateComments(outCore,dummyElt,"");
290 generateLibraries(outCore,dummyElt);
291 generateEntity(outCore);
292 generateArchitecture(outCore,dummyElt);
294 catch(Exception err) {
302 void GroupBlock::generateComments(QTextStream& out, QDomElement &elt, QString coreFile) throw(Exception) {
303 out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
306 void GroupBlock::generateLibraries(QTextStream& out, QDomElement &elt) throw(Exception) {
308 out << "library IEEE;" << endl;
309 out << "use IEEE.STD_LOGIC_1164.all;" << endl;
310 out << "use IEEE.numeric_std.all;" << endl;
314 void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {
318 for(i=0;i<indentLevel;i++) {
322 QList<BlockParameter*> listGenerics = getGenericParameters();
323 QList<AbstractInterface*> listInputs = getInputs();
324 QList<AbstractInterface*> listOutputs = getOutputs();
325 QList<AbstractInterface*> listBidirs = getBidirs();
327 if (!listGenerics.isEmpty()) {
328 out << indent << " generic (" << endl;
329 for(i=0;i<listGenerics.size()-1;i++) {
330 out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
332 out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
333 out << indent << " );" << endl;
336 out << indent << " port (" << endl;
338 // Generation of the clk & rst signals
339 out << indent << " -- clk/rst" << endl;
340 foreach(AbstractInterface* iface, listInputs) {
341 if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
342 out << indent << " " << iface->getName() << " : in std_logic;" << endl;
347 foreach(AbstractInterface* iface, getInterfaces()) {
348 if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;
350 // Generation of the data/control signals
355 foreach(AbstractInterface* iface, listInputs) {
356 if(iface->getPurpose() == AbstractInterface::Data) {
358 out << indent << " -- input data ports" << endl;
362 if (count == 0) flag = AbstractInterface::NoComma;
363 out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
367 foreach(AbstractInterface* iface, listInputs) {
368 if(iface->getPurpose() == AbstractInterface::Control) {
370 out << indent << " -- input control ports" << endl;
374 if (count == 0) flag = AbstractInterface::NoComma;
375 out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
379 foreach(AbstractInterface* iface, listOutputs) {
380 if(iface->getPurpose() == AbstractInterface::Data) {
382 out << indent << " -- output data ports" << endl;
386 if (count == 0) flag = AbstractInterface::NoComma;
387 out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
391 foreach(AbstractInterface* iface, listOutputs) {
392 if(iface->getPurpose() == AbstractInterface::Control) {
394 out << indent << " -- output control ports" << endl;
398 if (count == 0) flag = AbstractInterface::NoComma;
399 out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
403 foreach(AbstractInterface* iface, listBidirs) {
404 if(iface->getPurpose() == AbstractInterface::Data) {
406 out << indent << " -- bidirs data ports" << endl;
410 if (count == 0) flag = AbstractInterface::NoComma;
411 out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
414 out << indent << " );" << endl << endl;
417 void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {
421 out << "architecture rtl of " << name << " is " << endl << endl;
423 // generate the components
424 foreach(AbstractBlock* block, blocks) {
426 block->generateComponent(out,false);
435 out << " ----------------------------" << endl;
436 out << " SIGNALS" << endl;
437 out << " ----------------------------" << endl << endl;
439 out << " -- signals from input ports of " << name << endl;
440 QList<AbstractInterface*> listInputs = getInputs();
441 foreach(AbstractInterface* iface, listInputs) {
442 if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
443 ConnectedInterface* connIface = AI_TO_CON(iface);
444 QString prefixName = name+"_"+iface->getName()+"_TO_";
445 foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
446 QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
447 out << " signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
452 foreach(AbstractBlock* block, blocks) {
454 out << " -- signals from output ports of " << block->getName() << endl;
455 QList<AbstractInterface*> listOutputs = block->getOutputs();
456 foreach(AbstractInterface* iface, listOutputs) {
457 if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
458 ConnectedInterface* connIface = AI_TO_CON(iface);
459 QString prefixName = block->getName()+"_"+iface->getName()+"_TO_";
460 foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
461 QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
462 out << " signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
474 out << "end architecture rtl;" << endl;
477 void GroupBlock::generateController(QTextStream &out) throw(Exception) {