1 <!DOCTYPE logical_AND_3>
2 <block_impl ref_name="logical_AND_3.xml" ref_md5="">
4 <author lastname="" mail="" firstname=""/>
5 <date creation="2018-01-10"/>
6 <related_files list=""/>
7 <description>yt</description>
12 <package name="std_logic_1164" use="all"/>
13 <package name="numeric_std" use="all"/>
19 and_process : process (@{clk}, @{reset})
21 if @{reset} = '1' then
23 @{data_out} <= '0';
24 @{data_out_enb} <= '0';
26 elsif rising_edge(@{clk}) then
28 @{data_out} <= '0';
29 @{data_out_enb} <= '0';
31 if @{data1_in_enb} = '1' and @{data2_in_enb} = '1' and @{data3_in_enb} = '1' then
33 @{data_out} <= @{data1_in} and @{data2_in} and @{data3_in};
34 @{data_out_enb} <= '1';
39 end process and_process;
44 <input pattern="1" name="data1_in_enb"/>
45 <input pattern="1" name="data2_in_enb"/>
46 <input pattern="1" name="data3_in_enb"/>
48 <production counter="1">
49 <output pattern="01" name="data_out_enb"/>