lib/implementations/demux_impl.xml

   1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
   2 <block_impl ref_name="demux.xml" ref_md5="">
   3   <comments>
   4     <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
   5     <log creation="2018-05-02">
   6     </log>
   7     <notes>
   8     </notes>
   9   </comments>
  10
  11   <libraries>
  12     <library name="IEEE">
  13       <package name="std_logic_1164" use="all"/>
  14       <package name="numeric_std" use="all"/>
  15     </library>
  16   </libraries>
  17
  18   <architecture>
  19
  20     signal sel_s      : unsigned(@eval{@val{sel_width}-1} downto 0);
  21     signal val_i_dly  : std_logic_vector(@eval{@val{val_width}-1} downto 0};
  22
  23     @foreach{val_o}
  24     signal @{val_o}_enb : std_logic;
  25     @endforeach
  26
  27     begin
  28
  29     sel_s &lt;= @{sel_i};
  30
  31     delay_input : process(@{clk}, @{rst})
  32     begin
  33     if(@{rst}='1') then
  34       val_i_dly &lt;= (others => '0');
  35     elsif(rising_edge(@{clk})) then
  36       val_i_dly &lt;= @{val_i};
  37     end if;
  38     end process delay_input;
  39
  40
  41     demux : process(@{clk}, @{rst})
  42     begin
  43     if(@{rst}='1') then
  44
  45       @foreach{val_o}
  46       @{val_o}_enb &lt;= '0';
  47       @endforeach
  48
  49       elsif(rising_edge(@{clk})) then
  50
  51       @foreach{val_o}
  52       @{val_o}_enb &lt;= '0';
  53       @endforeach
  54
  55       @caseeach{val_o,sel_s,@#:1}
  56       @{val_o}_enb &lt;= '1';
  57       @endcaseeach
  58
  59       end if;
  60     end process demux;
  61
  62     @foreach{val_o}
  63     @{val_o}   &lt;= val_i_dly when (@{val_o}_enb = '1') else (others => '0');
  64     @endforeach
  65
  66   </architecture>
  67 </block_impl>