lib/implementations/multadd_impl.xml

   1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>\r
   2 <block_impl ref_name="multadd.xml" ref_md5="">\r
   3   <comments>\r
   4     <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />\r
   5     <log creation="2018-05-02">\r
   6     </log>\r
   7     <notes>\r
   8     </notes>    \r
   9   </comments>\r
  10 \r
  11   <libraries>\r
  12     <library name="IEEE">\r
  13       <package name="std_logic_1164" use="all"/>\r
  14       <package name="numeric_std" use="all"/>\r
  15     </library>\r
  16   </libraries>\r
  17 \r
  18   <architecture>\r
  19 \r
  20    -- Signals\r
  21   signal a_s      : signed(@eval{@val{in_width}-1} downto 0);\r
  22   signal b_s      : signed(@eval{@val{in_width}-1} downto 0);\r
  23   signal c_s      : signed(@eval{2*@val{in_width}-1} downto 0);\r
  24   signal result   : signed(@eval{2*@val{in_width}-1} downto 0);\r
  25 \r
  26 begin\r
  27 \r
  28   a_s &lt;= signed(@{a});\r
  29   b_s &lt;= signed(@{b});\r
  30   c_s &lt;= resize(signed(@{wb_c}),@eval{2*@val{in_width}});\r
  31   \r
  32   do_mult_process : process (@{clk}, @{rst})\r
  33   begin\r
  34     if @{rst} = '1' then\r
  35       \r
  36       result &lt;= to_signed(0,@eval{2*@val{in_width});\r
  37       \r
  38     elsif (rising_edge(@{clk})) then\r
  39 \r
  40       if @{wb_do_op} = '1' then\r
  41         result &lt;= a_s * b_s + c_s;\r
  42       end if;\r
  43       \r
  44     end if;\r
  45   end process do_mult_process;\r
  46 \r
  47   @{d} &lt;= std_logic_vector(result);\r
  48   @{wb_d} &lt;= std_logic_vector(resize(result,2*wb_data_width));\r
  49   \r
  50   </architecture>\r
  51   \r
  52 </block_impl>\r