lib/implementations/logical_AND_3_impl.xml

   1 <!DOCTYPE logical_AND_3>
   2 <block_impl ref_name="logical_AND_3.xml" ref_md5="">
   3   <comments>
   4     <author lastname="" mail="" firstname=""/>
   5     <log creation="2018-05-02">
   6     </log>
   7     <notes>
   8     </notes>
   9   </comments>
  10   <libraries>
  11     <library name="ieee">
  12       <package name="std_logic_1164" use="all"/>
  13       <package name="numeric_std" use="all"/>
  14     </library>
  15   </libraries>
  16   <architecture>
  17 begin
  18
  19 and_process : process (@{clk}, @{reset})
  20 begin
  21 if @{reset} = '1' then
  22
  23 @{data_out} &lt;= '0';
  24 @{data_out_enb} &lt;= '0';
  25
  26 elsif rising_edge(@{clk}) then
  27
  28 @{data_out} &lt;= '0';
  29 @{data_out_enb} &lt;= '0';
  30
  31 if @{data1_in_enb} = '1' and @{data2_in_enb} = '1' and @{data3_in_enb} = '1' then
  32
  33 @{data_out} &lt;= @{data1_in} and @{data2_in} and @{data3_in};
  34 @{data_out_enb} &lt;= '1';
  35
  36 end if;
  37 end if;
  38
  39 end process and_process;
  40 </architecture>
  41   <patterns>
  42     <delta value="1"/>
  43     <consumption>
  44       <input pattern="1" name="data1_in_enb"/>
  45       <input pattern="1" name="data2_in_enb"/>
  46       <input pattern="1" name="data3_in_enb"/>
  47     </consumption>
  48     <production counter="1">
  49       <output pattern="01" name="data_out_enb"/>
  50     </production>
  51   </patterns>
  52 </block_impl>