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debugged clk/rst auto conn
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1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>\r
2 <block>\r
3   <informations>\r
4     <name>\r
5       block demultiplexer\r
6     </name>\r
7     <category ids="1,5" />  \r
8     <description>\r
9       <brief>\r
10         This block demux an entry presented on FPGA pins over a variable number of outputs\r
11       </brief>\r
12       <detailed>\r
13         This block demux an entry presented on FPGA pins over a variable number of outputs\r
14       </detailed>     \r
15     </description>    \r
16   </informations>\r
17 \r
18   <parameters>\r
19     <parameter name="val_width" type="string" value="0" context="user"/>\r
20     <parameter name="sel_width" type="expression" value="$if_nb" iface="val_o" context="port"/>\r
21   </parameters>\r
22 \r
23   <interfaces>\r
24     <inputs>\r
25       <input name="clk" type="boolean" width="1" purpose="clock" />\r
26       <input name="rst" type="boolean" width="1" purpose="reset" />\r
27       \r
28       <input name="val_i" type="expression" width="$val_width" />\r
29       <input name="sel_i" type="expression" width="$sel_width" />\r
30     </inputs>\r
31     <outputs>\r
32       <output name="val_o" type="expression" width="$val_width" multiplicity="*"/>\r
33     </outputs>    \r
34   </interfaces>\r
35 \r
36 </block>\r