1 <!DOCTYPE deserializer_3x1>
2 <block_impl ref_name="deserializer_3x1.xml" ref_md5="">
4 <author lastname="" mail="" firstname=""/>
5 <log creation="2018-05-02">
13 <package name="std_logic_1164" use="all"/>
14 <package name="numeric_std" use="all"/>
19 signal do_out : std_logic;
20 signal data1_reg : std_logic_vector(in_width-1 downto 0);
21 signal data2_reg : std_logic_vector(in_width-1 downto 0);
23 signal count : unsigned(1 downto 0);
27 deser_process : process (@{clk}, @{reset})
29 if @{reset} = '1' then
30 count <= to_unsigned(0, 2);
31 data1_reg <= (others => '0');
32 data2_reg <= (others => '0');
33 @{data1_out} <= (others => '0');
34 @{data2_out} <= (others => '0');
35 @{data3_out} <= (others => '0');
38 elsif rising_edge(@{clk}) then
41 @{data1_out} <= (others => '0');
42 @{data2_out} <= (others => '0');
43 @{data3_out} <= (others => '0');
45 if @{data_in_enb} = '1' then
48 data1_reg <= @{data_in};
49 count <= count + 1;
51 data2_reg <= @{data_in};
52 count <= count + 1;
54 @{data1_out} <= data1_reg;
55 @{data2_out} <= data2_reg;
56 @{data3_out} <= @{data_in};
58 count <= to_unsigned(0, 2);
63 end process deser_process;
65 @{data1_out_enb} <= do_out;
66 @{data2_out_enb} <= do_out;
67 @{data3_out_enb} <= do_out;
72 <input pattern="111" name="data_in_enb"/>
74 <production counter="3">
75 <output pattern="0001" name="data1_out_enb"/>
76 <output pattern="0001" name="data2_out_enb"/>
77 <output pattern="0001" name="data3_out_enb"/>