// creating clk/rst interfaces
clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
- addInterface(clk);
- addInterface(rst);
+ addInterface(clk);
+ addInterface(rst);
+
+ try {
+ connectClkReset();
+ }
+ catch(Exception e) {
+ AbstractBlock* source = (AbstractBlock *)(e.getSource());
+ cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+ throw(e);
+ }
}
else {
topGroup = true;
}
-void GroupBlock::generateEntity(QTextStream& out, bool hasController) throw(Exception) {
+void GroupBlock::generateEntityOrComponentBody(QTextStream& out, int indentLevel, bool hasController) throw(Exception) {
int i;
-
- out << "entity " << name << " is " << endl;
+ QString indent = "";
+ for(i=0;i<indentLevel;i++) {
+ indent += " ";
+ }
QList<BlockParameter*> listGenerics = getGenericParameters();
QList<AbstractInterface*> listInputs = getInputs();
QList<AbstractInterface*> listBidirs = getBidirs();
if (!listGenerics.isEmpty()) {
- out << " generic (" << endl;
+ out << indent << " generic (" << endl;
for(i=0;i<listGenerics.size()-1;i++) {
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
}
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
- out << " );" << endl;
+ out << indent << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+ out << indent << " );" << endl;
}
- out << " port (" << endl;
+ out << indent << " port (" << endl;
// Generation of the clk & rst signals
- out << " -- clk/rst" << endl;
+ out << indent << " -- clk/rst" << endl;
foreach(AbstractInterface* iface, listInputs) {
if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
- out << " " << iface->getName() << " : in std_logic;" << endl;
+ out << indent << " " << iface->getName() << " : in std_logic;" << endl;
}
}
foreach(AbstractInterface* iface, listInputs) {
if(iface->getPurpose() == AbstractInterface::Data) {
if (first) {
- out << " -- input data ports" << endl;
+ out << indent << " -- input data ports" << endl;
first = false;
}
count--;
if (count == 0) flag = AbstractInterface::NoComma;
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
}
}
first = true;
foreach(AbstractInterface* iface, listInputs) {
if(iface->getPurpose() == AbstractInterface::Control) {
if (first) {
- out << " -- input control ports" << endl;
+ out << indent << " -- input control ports" << endl;
first = false;
}
count--;
if (count == 0) flag = AbstractInterface::NoComma;
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
}
}
first = true;
foreach(AbstractInterface* iface, listOutputs) {
if(iface->getPurpose() == AbstractInterface::Data) {
if (first) {
- out << " -- output data ports" << endl;
+ out << indent << " -- output data ports" << endl;
first = false;
}
count--;
if (count == 0) flag = AbstractInterface::NoComma;
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
}
}
first = true;
foreach(AbstractInterface* iface, listOutputs) {
if(iface->getPurpose() == AbstractInterface::Control) {
if (first) {
- out << " -- output control ports" << endl;
+ out << indent << " -- output control ports" << endl;
first = false;
}
count--;
if (count == 0) flag = AbstractInterface::NoComma;
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
}
}
first = true;
foreach(AbstractInterface* iface, listBidirs) {
if(iface->getPurpose() == AbstractInterface::Data) {
if (first) {
- out << " -- bidirs data ports" << endl;
+ out << indent << " -- bidirs data ports" << endl;
first = false;
}
count--;
if (count == 0) flag = AbstractInterface::NoComma;
- out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ out << indent << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
}
}
- out << " );" << endl << endl;
- out << "end " << name << ";" << endl << endl;
-
+ out << indent << " );" << endl << endl;
}
void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(Exception) {
+ int i;
+
+ out << "architecture rtl of " << name << " is " << endl << endl;
+
+ // generate the components
+ foreach(AbstractBlock* block, blocks) {
+ try {
+ block->generateComponent(out,false);
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ }
+
+ out << endl;
+ // generate signals
+ out << " ----------------------------" << endl;
+ out << " SIGNALS" << endl;
+ out << " ----------------------------" << endl << endl;
+
+
+ foreach(AbstractBlock* block, blocks) {
+ try {
+ out << " -- signals from output ports of " << block->getName() << endl;
+ QList<AbstractInterface*> listOutputs = block->getOutputs();
+ foreach(AbstractInterface* iface, listOutputs) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+ }
+ else if (block->getName() == "clkrstgen") {
+ if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
+ out << " signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+ }
+ }
+ }
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ out << endl;
+ }
+ foreach(AbstractBlock* block, blocks) {
+ try {
+ out << " -- signals for modified input ports of " << block->getName() << endl;
+ QList<AbstractInterface*> listInputs = block->getInputs();
+ foreach(AbstractInterface* iface, listInputs) {
+ if (iface->getPurpose() == AbstractInterface::Control) {
+ ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+ AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+ if (modifier != NULL) {
+ out << modifier->toVHDL(AbstractInputModifier::Signal,0) << endl;
+ }
+ }
+ }
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ out << endl;
+ }
+
+ out << "begin" << endl;
+
+ // generate signals that goes to the output ports
+
+ out << " -- connections to output ports of " << name << endl;
+ QList<AbstractInterface*> listOutputs = getOutputs();
+ foreach(AbstractInterface* iface, listOutputs) {
+ if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+ ConnectedInterface* connIface = AI_TO_CON(iface);
+ ConnectedInterface* fromIface = connIface->getConnectedFrom();
+ out << " " << connIface->getName() << " <= " << fromIface->toVHDL(AbstractInterface::Instance,0) << ";" << endl;
+ }
+ }
+
+ out << endl;
+
+
+
+ // generate instances
+ foreach(AbstractBlock* block, blocks) {
+ try {
+ out << " " << block->getName() << "_1 : " << block->getName() << endl;
+
+ QList<BlockParameter*> listGenerics = block->getGenericParameters();
+ QList<AbstractInterface*> listInputs = block->getInputs();
+ QList<AbstractInterface*> listOutputs = block->getOutputs();
+ QList<AbstractInterface*> listBidirs = block->getBidirs();
+
+ if (!listGenerics.isEmpty()) {
+ out << " generic map (" << endl;
+ for(i=0;i<listGenerics.size()-1;i++) {
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Instance, BlockParameter::NoComma) << "," << endl;
+ }
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Instance,BlockParameter::NoComma) << endl;
+ out << " )" << endl;
+ }
+
+ out << " port map (" << endl;
+ QString portMap = "";
+
+ for(i=0;i<listInputs.size();i++) {
+ ConnectedInterface* connIface = AI_TO_CON(listInputs.at(i));
+ ConnectedInterface* fromIface = connIface->getConnectedFrom();
+
+ if (fromIface->isFunctionalInterface()) {
+ portMap += " " + connIface->getName() + " => ";
+ bool hasMod = false;
+ if (connIface->getPurpose() == AbstractInterface::Data) {
+ ConnectedInterface* connCtlIface = AI_TO_CON(connIface->getAssociatedIface());
+ if ((connCtlIface != NULL) && (connCtlIface->getInputModifier() != NULL)) {
+ hasMod = true;
+ }
+ }
+ else if (connIface->getPurpose() == AbstractInterface::Control) {
+ if (connIface->getInputModifier() != NULL) {
+ hasMod = true;
+ }
+ }
+ if (hasMod) {
+ portMap += connIface->getOwner()->getName()+"_"+connIface->getName()+"_mod,\n";
+ }
+ else {
+ portMap += fromIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+ }
+ }
+ else if (fromIface->isGroupInterface()) {
+ portMap += " " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+ }
+ }
+ if (listOutputs.size()>0) {
+ for(i=0;i<listOutputs.size();i++) {
+ ConnectedInterface* connIface = AI_TO_CON(listOutputs.at(i));
+ portMap += " " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+ }
+ }
+ if (listBidirs.size()>0) {
+ for(i=0;i<listBidirs.size();i++) {
+ ConnectedInterface* connIface = AI_TO_CON(listBidirs.at(i));
+ portMap += " " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+ }
+ }
+ portMap.chop(2);
+ out << portMap << endl;
+
+
+ out << " );" << endl;
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ out << endl;
+ }
+
+ // generate input modifiers
+ foreach(AbstractBlock* block, blocks) {
+
+ foreach(AbstractInterface* iface, block->getControlInputs()) {
+ ConnectedInterface* connIface = AI_TO_CON(iface);
+ // check if it is connected
+ if (connIface->getConnectedFrom() == NULL) {
+ throw(Exception(IFACE_NOT_CONNECTED,this));
+ }
+ AbstractInputModifier* modifier = connIface->getInputModifier();
+ if (modifier != NULL) {
+ try {
+ out << modifier->toVHDL(AbstractInputModifier::Architecture,0) << endl;
+ }
+ catch(Exception e) {
+ throw(e);
+ }
+ }
+ }
+ }
+
+ out << "end architecture rtl;" << endl;
}
void GroupBlock::generateController(QTextStream &out) throw(Exception) {
