finished VHDL gen

[blast.git] / Dispatcher.cpp

diff --git a/Dispatcher.cpp b/Dispatcher.cpp
index b9e09a946151f447a71b6eb287cffa586f6fe39b..cdf8ee3b1c281ba5381bb56b605440f2de7a698e 100644 (file)
--- a/Dispatcher.cpp
+++ b/Dispatcher.cpp
@@ -256,11 +256,18 @@ void Dispatcher::generateVHDL() throw(Exception) {
   }
   out << endl;
   out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
-  out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+  out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl;
+  out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
   out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
 
   paramFile.close();
 
+  QString msg = "VHDL generation completed successfully. Go to ";
+  msg += params->projectPath+" and type the following commands to launch a simulation:\n";
+  msg += "\tmake clean\n";
+  msg += "\tmake\n";
+  msg += "\tmake view\n";
+  QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok);
 
 }