<package name="numeric_std" use="all"/>
</library>
</libraries>
- <architecture>
+ <architecture comp_list="mult_accum">
component mult_accum
port (
@{clk} : in std_logic;
signal do_sum_cr_dly : std_logic;
signal do_sum_cb : std_logic;
signal do_sum_cb_dly : std_logic;
-signal do_out : std_logic;
signal do_out_cr : std_logic;
signal do_out_cb : std_logic;
signal do_out_y : std_logic;
signal b_cb : std_logic_vector(17 downto 0);
signal s_cb : std_logic_vector(47 downto 0);
-signal compo_out : std_logic_vector(7 downto 0);
-
begin
y_multiplier : mult_accum
sumy_process : process (@{clk}, @{reset})
begin
if @{reset} = '1' then
-bypass_y <= '0';
+bypass_y <= '1';
+do_sum_y_dly <= '0';
y <= to_signed(0, 9);
y_dly1 <= to_signed(0, 9);
y_dly2 <= to_signed(0, 9);
sumcb_process : process (@{clk}, @{reset})
begin
if @{reset} = '1' then
-bypass_cb <= '0';
+bypass_cb <= '1';
+do_sum_cb_dly <= '0';
cb <= to_signed(0, 9);
cb_dly1 <= to_signed(0, 9);
elsif rising_edge(@{clk}) then
sumcr_process : process (@{clk}, @{reset})
begin
if @{reset} = '1' then
-bypass_cr <= '0';
+bypass_cr <= '1';
+do_sum_cr_dly <= '0';
cr <= to_signed(0, 9);
do_out_cr <= '0';
std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
(others => '0');
@{ycbcr_out_enb} <= do_out_y or do_out_cb or do_out_cr;
-
-end rtl;
</architecture>
<patterns>
<delta value="3"/>
