nearly finished GroupBlock VHDL gen

[blast.git] / VHDLConverter.cpp

diff --git a/VHDLConverter.cpp b/VHDLConverter.cpp
index 42fff3a7467329d58791e259f6d91b6f8acc37ed..88b371f01440213679c51c2b42927ba2486a97c5 100644 (file)
--- a/VHDLConverter.cpp
+++ b/VHDLConverter.cpp
@@ -459,12 +459,12 @@ void VHDLConverter::loadVHDLFile() {
     else {\r
       widthStr = "std_logic_vector(";\r
       if (iface->getEndianess() == AbstractInterface::LittleEndian) {\r
-        widthStr += iface->getWidth();\r
+        widthStr += iface->getWidthString();\r
         widthStr += " downto 0)";\r
       }\r
       else {\r
         widthStr += "0 to ";\r
-        widthStr += iface->getWidth();\r
+        widthStr += iface->getWidthString();\r
         widthStr += ")";\r
       }\r
     }\r
@@ -651,7 +651,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement input = doc.createElement("input");\r
         input.setAttribute("name",iface->getName());\r
         input.setAttribute("type",iface->getTypeString());\r
-        input.setAttribute("width",iface->getWidth());\r
+        input.setAttribute("width",iface->getWidthString());\r
         input.setAttribute("multiplicity","1");\r
         input.setAttribute("purpose",iface->getPurposeString());\r
         input.setAttribute("endian",iface->getEndianessString());\r
@@ -673,7 +673,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement output = doc.createElement("output");\r
         output.setAttribute("name",iface->getName());\r
         output.setAttribute("type",iface->getTypeString());\r
-        output.setAttribute("width",iface->getWidth());\r
+        output.setAttribute("width",iface->getWidthString());\r
         output.setAttribute("multiplicity","1");\r
         output.setAttribute("purpose",iface->getPurposeString());\r
         output.setAttribute("endian",iface->getEndianessString());\r
@@ -695,7 +695,7 @@ void VHDLConverter::generateRefXml(QDomDocument& doc) {
         QDomElement bidir = doc.createElement("bidir");\r
         bidir.setAttribute("name",iface->getName());\r
         bidir.setAttribute("type",iface->getTypeString());\r
-        bidir.setAttribute("width",iface->getWidth());\r
+        bidir.setAttribute("width",iface->getWidthString());\r
         bidir.setAttribute("multiplicity","1");\r
         bidir.setAttribute("purpose",iface->getPurposeString());\r
         bidir.setAttribute("endian",iface->getEndianessString());\r
@@ -826,11 +826,12 @@ void VHDLConverter::replaceSignalNames(QString& line) {
 void VHDLConverter::updateArchitecture() {\r
   QRegularExpression rxLT("<=",QRegularExpression::CaseInsensitiveOption);\r
   QRegularExpression rxGT("=>",QRegularExpression::CaseInsensitiveOption);\r
-  foreach(QString line, archLines) {\r
+  for(int i=0;i<archLines.size();i++) {\r
+    QString line = archLines.at(i);\r
     replaceSignalNames(line);\r
-    line.replace(rxLT,"&lt;=");\r
-    line.replace(rxGT,"=&gt;");\r
-\r
+    //line.replace(rxLT,"&lt;=");\r
+    //line.replace(rxGT,"=&gt;");\r
+    archLines.replace(i,line);\r
     cout << qPrintable(line) << endl;\r
   }\r
 }\r