started top group gen, added project subdirs

[blast.git] / VHDLConverter.cpp

diff --git a/VHDLConverter.cpp b/VHDLConverter.cpp
index 42fff3a7467329d58791e259f6d91b6f8acc37ed..d3938b29e453c4fca1f19ec7a22b9c07af1a8760 100644 (file)
--- a/VHDLConverter.cpp
+++ b/VHDLConverter.cpp
@@ -826,11 +826,12 @@ void VHDLConverter::replaceSignalNames(QString& line) {
 void VHDLConverter::updateArchitecture() {\r
   QRegularExpression rxLT("<=",QRegularExpression::CaseInsensitiveOption);\r
   QRegularExpression rxGT("=>",QRegularExpression::CaseInsensitiveOption);\r
 void VHDLConverter::updateArchitecture() {\r
   QRegularExpression rxLT("<=",QRegularExpression::CaseInsensitiveOption);\r
   QRegularExpression rxGT("=>",QRegularExpression::CaseInsensitiveOption);\r

-  foreach(QString line, archLines) {\r
+  for(int i=0;i<archLines.size();i++) {\r
+    QString line = archLines.at(i);\r

     replaceSignalNames(line);\r
     replaceSignalNames(line);\r

-    line.replace(rxLT,"&lt;=");\r
-    line.replace(rxGT,"=&gt;");\r
-\r
+    //line.replace(rxLT,"&lt;=");\r
+    //line.replace(rxGT,"=&gt;");\r
+    archLines.replace(i,line);\r

     cout << qPrintable(line) << endl;\r
   }\r
 }\r
     cout << qPrintable(line) << endl;\r
   }\r
 }\r