started top group gen, added project subdirs

diff --git a/top_group.vhd b/top_group.vhd
deleted file mode 100644 (file)
index 60ae10f..0000000
--- a/top_group.vhd
+++ /dev/null
@@ -1,22 +0,0 @@
- -- VHDL generated automatically for top_group --
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.numeric_std.all;
-entity top_group is 
-  port (
-    -- clk/rst
-    ext_clk : in std_logic;
-    ext_reset : in std_logic;
-    -- input data ports
-    
-    -- input control ports
-    
-    -- output data ports
-    
-    -- output control ports
-    
-    );
-
-end top_group;
-