nearly finished GroupBlock VHDL gen

[blast.git] / GroupBlock.cpp

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 9a8bb0f857df75dd5843ad5069cc80aa27f852fb..66268b93e161d8bc76d0d4061b65f5f07af30e4d 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -21,8 +21,17 @@ GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) :  AbstractBlock()
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);
     // creating clk/rst interfaces
     clk = new GroupInterface(this,"clk", AbstractInterface::Input, AbstractInterface::Clock);
     rst = new GroupInterface(this,"reset", AbstractInterface::Input, AbstractInterface::Reset);

-    addInterface(clk);
-    addInterface(rst);    
+    addInterface(clk);    
+    addInterface(rst);
+
+    try {
+      connectClkReset();
+    }
+    catch(Exception e) {
+      AbstractBlock* source = (AbstractBlock *)(e.getSource());
+      cerr << qPrintable(source->getName()) << ":" << qPrintable(e.getMessage()) << endl;
+      throw(e);
+    }

   }
   else {
     topGroup = true;
   }
   else {
     topGroup = true;


@@ -436,33 +445,133 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << "    SIGNALS" << endl;
   out << "  ----------------------------" << endl << endl;
 
   out << "    SIGNALS" << endl;
   out << "  ----------------------------" << endl << endl;
 

-  out << "  -- signals from input ports of " << name << endl;
-  QList<AbstractInterface*> listInputs = getInputs();
-  foreach(AbstractInterface* iface, listInputs) {
+
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  -- signals from output ports of " << block->getName() << endl;
+      QList<AbstractInterface*> listOutputs = block->getOutputs();
+      foreach(AbstractInterface* iface, listOutputs) {
+        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+          out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+        }
+        else if (block->getName() == "clkrstgen") {
+          if ((iface->getPurpose() == AbstractInterface::Clock)||(iface->getPurpose() == AbstractInterface::Reset)) {
+            out << "  signal " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+  foreach(AbstractBlock* block, blocks) {
+    try {
+      out << "  -- signals for modified input ports of " << block->getName() << endl;
+      QList<AbstractInterface*> listInputs = block->getInputs();
+      foreach(AbstractInterface* iface, listInputs) {
+        if (iface->getPurpose() == AbstractInterface::Control) {
+          ConnectedInterface* connCtlIface = AI_TO_CON(iface);
+          AbstractInputModifier* modifier = connCtlIface->getInputModifier();
+          if (modifier != NULL) {
+            out << modifier->toVHDL(AbstractInputModifier::Signal,0) << endl;
+          }
+        }
+      }
+    }
+    catch(Exception e) {
+      throw(e);
+    }
+    out << endl;
+  }
+
+  out << "begin" << endl;
+
+  // generate signals that goes to the output ports
+
+  out << "  -- connections to output ports of " << name << endl;
+  QList<AbstractInterface*> listOutputs = getOutputs();
+  foreach(AbstractInterface* iface, listOutputs) {

     if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
       ConnectedInterface* connIface = AI_TO_CON(iface);
     if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
       ConnectedInterface* connIface = AI_TO_CON(iface);

-      QString prefixName = name+"_"+iface->getName()+"_TO_";
-      foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
-        QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
-        out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
-      }
+      ConnectedInterface* fromIface = connIface->getConnectedFrom();
+      out << "  " << connIface->getName() << " <= " << fromIface->toVHDL(AbstractInterface::Instance,0) << ";" << endl;

     }
   }
     }
   }

+

   out << endl;
   out << endl;

+
+
+
+  // generate instances

   foreach(AbstractBlock* block, blocks) {
     try {
   foreach(AbstractBlock* block, blocks) {
     try {

-      out << "  -- signals from output ports of " << block->getName() << endl;
+      out << "  " << block->getName() << "_1 : " << block->getName() << endl;
+
+      QList<BlockParameter*> listGenerics = block->getGenericParameters();
+      QList<AbstractInterface*> listInputs = block->getInputs();

       QList<AbstractInterface*> listOutputs = block->getOutputs();
       QList<AbstractInterface*> listOutputs = block->getOutputs();

-      foreach(AbstractInterface* iface, listOutputs) {
-        if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
-          ConnectedInterface* connIface = AI_TO_CON(iface);
-          QString prefixName = block->getName()+"_"+iface->getName()+"_TO_";
-          foreach(ConnectedInterface* toIface, connIface->getConnectedTo()) {
-            QString sigName = prefixName+toIface->getOwner()->getName()+"_"+toIface->getName();
-            out << "  signal " << sigName << " : " << iface->toVHDL(AbstractInterface::Signal,0) << endl;
+      QList<AbstractInterface*> listBidirs = block->getBidirs();
+
+      if (!listGenerics.isEmpty()) {
+        out << "    generic map (" << endl;
+        for(i=0;i<listGenerics.size()-1;i++) {
+          out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance, BlockParameter::NoComma) << "," << endl;
+        }
+        out << "      " << listGenerics.at(i)->toVHDL(BlockParameter::Instance,BlockParameter::NoComma) << endl;
+        out << "    )" << endl;
+      }
+
+      out << "    port map (" << endl;
+      QString portMap = "";
+
+      for(i=0;i<listInputs.size();i++) {
+        ConnectedInterface* connIface = AI_TO_CON(listInputs.at(i));
+        ConnectedInterface* fromIface = connIface->getConnectedFrom();
+
+        if (fromIface->isFunctionalInterface()) {
+          portMap += "      " + connIface->getName() + " => ";
+          bool hasMod = false;
+          if (connIface->getPurpose() == AbstractInterface::Data) {
+            ConnectedInterface* connCtlIface = AI_TO_CON(connIface->getAssociatedIface());
+            if ((connCtlIface != NULL) && (connCtlIface->getInputModifier() != NULL)) {
+              hasMod = true;
+            }
+          }
+          else if (connIface->getPurpose() == AbstractInterface::Control) {
+            if (connIface->getInputModifier() != NULL) {
+              hasMod = true;
+            }

           }
           }

+          if (hasMod) {
+            portMap += connIface->getOwner()->getName()+"_"+connIface->getName()+"_mod,\n";
+          }
+          else {
+            portMap += fromIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+          }
+        }
+        else if (fromIface->isGroupInterface()) {
+          portMap += "      " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+        }
+      }
+      if (listOutputs.size()>0) {
+        for(i=0;i<listOutputs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listOutputs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";
+        }
+      }
+      if (listBidirs.size()>0) {
+        for(i=0;i<listBidirs.size();i++) {
+          ConnectedInterface* connIface = AI_TO_CON(listBidirs.at(i));
+          portMap += "      " + connIface->getName() + " => " + connIface->toVHDL(AbstractInterface::Instance, AbstractInterface::NoComma) + ",\n";

         }
       }
         }
       }

+      portMap.chop(2);
+      out << portMap << endl;
+
+
+      out << "    );" << endl;

     }
     catch(Exception e) {
       throw(e);
     }
     catch(Exception e) {
       throw(e);


@@ -470,6 +579,26 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
     out << endl;
   }
 
     out << endl;
   }
 

+  // generate input modifiers
+  foreach(AbstractBlock* block, blocks) {
+
+    foreach(AbstractInterface* iface, block->getControlInputs()) {
+      ConnectedInterface* connIface = AI_TO_CON(iface);
+      // check if it is connected
+      if (connIface->getConnectedFrom() == NULL) {
+        throw(Exception(IFACE_NOT_CONNECTED,this));
+      }
+      AbstractInputModifier* modifier = connIface->getInputModifier();
+      if (modifier != NULL) {
+        try {
+          out << modifier->toVHDL(AbstractInputModifier::Architecture,0) << endl;
+        }
+        catch(Exception e) {
+          throw(e);
+        }
+      }
+    }
+  }

 
   out << "end architecture rtl;" << endl;
 }
 
   out << "end architecture rtl;" << endl;
 }