finished conn mode of library

[blast.git] / DelayInputModifier.cpp

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index a90695a2ecdb6737b92a547ffa527d1e86c666cd..db89107a4614a9a9bad39bde1cac761a8c562329 100644 (file)
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -29,28 +29,35 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
   ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());\r
   QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();\r
   QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();\r
   ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());\r
   QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();\r
   QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();\r

-  QString dm1 = "";\r

   QString dm2 = "";\r
   QString dm2 = "";\r

-  dm1.setNum(delayLength-1);\r
+  QString dm3 = "";\r

   dm2.setNum(delayLength-2);\r
   dm2.setNum(delayLength-2);\r

+  dm3.setNum(delayLength-3);\r

   QString ret="";\r
   QString ret="";\r

+  QString clkName = "clk";\r
+  QString resetName = "reset";\r
+  if (toIface->getOwner()->getParent()->isTopGroupBlock()) {\r
+    clkName = "from_clkrstgen_clk";\r
+    resetName ="from_clkrstgen_reset";\r
+  }\r
+\r

   if (context == Architecture) {\r
   if (context == Architecture) {\r

-    ret = toName + "_mod_process : process(clk,reset)\n";\r
+    ret = toName + "_mod_process : process("+clkName+","+resetName+")\n";\r

     ret += "  begin\n";\r
     ret += "  begin\n";\r

-    ret += "    if reset = '1' then\n";\r
+    ret += "    if "+resetName+" = '1' then\n";\r

     ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";\r
     ret += "      "+toCtlName+"_dly  <= (others => '0');\n";\r
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r
     ret += "      "+toName+"_dly     <= (others => (others => '0'));\n";\r
     ret += "      "+toCtlName+"_dly  <= (others => '0');\n";\r
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r

-    ret += "    elsif rising_edge(clk) then\n";\r
-    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";\r
-    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";\r
+    ret += "    elsif rising_edge("+clkName+") then\n";\r
+    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm2+");\n";\r
+    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm2+");\n";\r

     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r

-    ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";\r
-    ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";\r
-    ret += "    end if\n";\r
-    ret += "  end process "+toName + "_mod_process\n";\r
+    ret += "      "+toName+"_dly(1 to "+dm2+")  <= "+toName+"_dly(0 to "+dm3+");\n";\r
+    ret += "      "+toCtlName+"_dly(1 to "+dm2+")  <= "+toCtlName+"_dly(0 to "+dm3+");\n";\r
+    ret += "    end if;\n";\r
+    ret += "  end process "+toName + "_mod_process;\n";\r

   }\r
   else if (context == Signal) {\r
     QString sig = toIface->toVHDL(AbstractInterface::Signal,0);\r
   }\r
   else if (context == Signal) {\r
     QString sig = toIface->toVHDL(AbstractInterface::Signal,0);\r


@@ -61,8 +68,8 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "  signal "+sig+"\n";\r
     QString wStr="";\r
     wStr.setNum(toIface->getWidth());\r
     ret += "  signal "+sig+"\n";\r
     QString wStr="";\r
     wStr.setNum(toIface->getWidth());\r

-    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm1+");\n";\r
-    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm1+");\n";\r
+    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n";\r
+    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm2+");\n";\r

   }\r
 \r
   return ret;\r
   }\r
 \r
   return ret;\r