virtual bool isGroupBlock();\r
virtual bool isStimuliBlock(); //! a stimuli block is outside the top group and simulates a peripheral (NB: this is also a source)\r
virtual bool isTopGroupBlock();\r
- bool isSourceBlock(); //! a source block has no data inputs and thus executes infinitely\r
+ bool isSourceBlock(); //! a source block is either a block that has no data inputs or that is of special type source. Thus it executes infinitely\r
bool isSinkBlock(); //! a sink block has no data outputs and just collects what it receives (i.e. no compatibility check)\r
bool isWBConfigurable();\r
\r
* \brief connectClkReset connects the clock and reset inputs to a clkrstgen block or the the group ifaces\r
* \param idBlockClk is the id of the clock interface (there may be severals)\r
* \param idGen is the id of the clkrstgen block\r
- */\r
- void connectClock(QString clkName, int idGen = 0) throw(Exception);\r
- void connectReset(QString rstName, int idGen = 0) throw(Exception);\r
+ */ \r
virtual QList<QString> getExternalResources() = 0; // returns the list of all external files needed for VHDL generation\r
virtual void generateVHDL(const QString& path) throw(Exception) = 0; // main entry to generate the VHDL code\r
void generateComponent(QTextStream& out, bool hasController=false) throw(Exception); // generate the component using reference\r
