-\r
- if (hasController) {\r
- // Generation of the wishbone signals\r
- out << " -- registers r/w via wishbone" << endl;\r
- QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
- for(i=0;i<listWB.size()-1;i++) {\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0);\r
- }\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma);\r
- }\r
-\r
-\r
- // Generation of the data signals\r
- out << "-- data ports\n";\r
- for(int i = 0; i < listInputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName()));\r
- if(listInputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listInputs.at(i)->getWidth());\r
- if(listInputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
- }\r
-\r
- for(int i = 0; i < listOutputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName()));\r
- if(listOutputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listOutputs.at(i)->getWidth());\r
- if(listOutputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
- }\r
-\r
- for(int i = 0; i < listBidirs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName()));\r
- if(listBidirs.at(i)->getWidth().compare(("1")))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth((listBidirs.at(i)->getWidth()));\r
- if(listBidirs.at(i)->getPurpose() == 1)\r
- out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
- }\r
-}\r
-\r
-// This function generates the architecture part of the VHDL document\r
-void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) {\r
-\r
- QString expr;\r
- QDomElement eltArch = elt.nextSiblingElement("architecture");\r
- out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n";\r
- QString implText = eltArch.text();\r
- QStringList listLine = implText.split("\n");\r
- for(int i =0; i < listLine.size(); i++) {\r
- if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) {\r
- while(listLine.at(i).compare("@endforeach") != -1) {\r
- expr = expr + listLine.at(i) + '\n';\r
- i++;\r
- }\r
- expr = expr + listLine.at(i);\r
- out << evalComplex(expr, 1) << '\n';\r