modif in VHDLConverter

[blast.git] / lib / implementations / multadd_impl.xml

diff --git a/lib/implementations/multadd_impl.xml b/lib/implementations/multadd_impl.xml
index fc2d10f785eba295da5703dd6a7c8a08ce35953f..74a022a3207db0beb475b904143c447e33bb1045 100644 (file)
--- a/lib/implementations/multadd_impl.xml
+++ b/lib/implementations/multadd_impl.xml
@@ -2,7 +2,7 @@
 <block_impl ref_name="multadd.xml" ref_md5="">\r
   <comments>\r
     <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />\r
 <block_impl ref_name="multadd.xml" ref_md5="">\r
   <comments>\r
     <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />\r

-    <date creation="2015/04/27" />\r
+    <date creation="2015-04-27" />\r

     <related_files list=""/>\r
     <description>\r
       This component is a multadd\r
     <related_files list=""/>\r
     <description>\r
       This component is a multadd\r


@@ -52,12 +52,5 @@ begin
   @{wb_d} &lt;= std_logic_vector(resize(result,2*wb_data_width));\r
   \r
   </architecture>\r
   @{wb_d} &lt;= std_logic_vector(resize(result,2*wb_data_width));\r
   \r
   </architecture>\r

-\r
-  <patterns>\r
-    <parameters>\r
-      <parameter name="m" value="1" />\r
-    </parameters>    \r
-    <delta value="1" />\r
-  </patterns>\r

   \r
 </block_impl>\r
   \r
 </block_impl>\r