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--- /dev/null
+<!DOCTYPE rgb3sx8_to_gs>
+<block_impl ref_md5="" ref_name="rgb3sx8_to_gs.xml">
+ <comments>
+ <author mail="" lastname="" firstname=""/>
+ <date creation=""/>
+ <description>vcdsv</description>
+ <notes>vrevgfregaqv</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+-- Signals
+signal do_mult : std_logic;
+signal do_out : std_logic;
+signal count : unsigned (2 downto 0);
+signal accum : unsigned(dsp_in_width-1 downto 0);
+signal result : unsigned(dsp_out_width-1 downto 0);
+signal cst_mult : unsigned(dsp_in_width-1 downto 0); -- eq. 87382 to do /3
+
+begin
+
+cst_mult <= to_unsigned(87382, 18);
+
+accum_process : process (clk, reset)
+begin
+if reset = '1' then
+count <= to_unsigned(0, 3);
+accum <= to_unsigned(0, dsp_in_width);
+do_mult <= '0';
+
+elsif rising_edge(clk) then
+
+do_mult <= '0';
+
+if rgb_in_enb = '1' then
+
+if count = 0 then
+accum <= resize(unsigned(rgb_in), dsp_in_width);
+count <= to_unsigned(1, 3);
+elsif count = 1 then
+accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+count <= to_unsigned(2, 3);
+elsif count = 2 then
+accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+count <= to_unsigned(0, 3);
+do_mult <= '1';
+end if;
+end if;
+end if;
+
+end process accum_process;
+
+mult_process : process (clk, reset)
+begin
+if reset = '1' then
+result <= to_unsigned(0, dsp_out_width);
+do_out <= '0';
+elsif rising_edge(clk) then
+
+do_out <= '0';
+if do_mult = '1' then
+result <= accum * cst_mult;
+do_out <= '1';
+end if;
+end if;
+end process mult_process;
+
+gs_out <= std_logic_vector(result(dsp_in_width+7 downto dsp_in_width));
+gs_out_enb <= do_out;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="to_define"/>
+ <consumption>
+ <input name="rgb_in_enb" pattern="to_define"/>
+ </consumption>
+ <production counter="to_define">
+ <output name="gs_out_enb" pattern="to_define"/>
+ </production>
+ </patterns>
+</block_impl>