+}
+
+void GroupBlock::generateVHDL(const QString& path) throw(Exception) {
+
+ QString coreFile = "";
+
+ coreFile = path;
+ coreFile.append(normalizeName(name));
+ coreFile.append(".vhd");
+
+ QFile vhdlCore(coreFile);
+
+ if (!vhdlCore.open(QIODevice::WriteOnly)) {
+ throw(Exception(VHDLFILE_NOACCESS));
+ }
+
+ QTextStream outCore(&vhdlCore);
+
+ try {
+ generateComments(outCore);
+ generateLibraries(outCore);
+ generateEntity(outCore);
+ generateArchitecture(outCore);
+ }
+ catch(Exception err) {
+ throw(err);
+ }
+
+ vhdlCore.close();
+}
+
+
+void GroupBlock::generateComments(QTextStream& out) throw(Exception) {
+ out << " -- VHDL generated automatically for " << name << " --" << endl << endl;
+}
+
+void GroupBlock::generateLibraries(QTextStream& out) throw(Exception) {
+
+ out << "library IEEE;" << endl;
+ out << "use IEEE.STD_LOGIC_1164.all;" << endl;
+ out << "use IEEE.numeric_std.all;" << endl;
+
+}
+
+void GroupBlock::generateEntity(QTextStream& out) throw(Exception) {
+
+ int i;
+
+ out << "entity " << name << " is " << endl;
+
+ QList<BlockParameter*> listGenerics = getGenericParameters();
+ QList<AbstractInterface*> listInputs = getInputs();
+ QList<AbstractInterface*> listOutputs = getOutputs();
+ QList<AbstractInterface*> listBidirs = getBidirs();
+
+ if (!listGenerics.isEmpty()) {
+ out << " generic (" << endl;
+ for(i=0;i<listGenerics.size()-1;i++) {
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;
+ }
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;
+ out << " );" << endl;
+ }
+
+ out << " port (" << endl;
+
+ // Generation of the clk & rst signals
+ out << " -- clk/rst" << endl;
+ foreach(AbstractInterface* iface, listInputs) {
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {
+ out << " " << iface->getName() << " : in std_logic;" << endl;
+ }
+ }
+
+ int count = 0;
+ foreach(AbstractInterface* iface, getInterfaces()) {
+ if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;
+ }
+ // Generation of the data/control signals
+
+ int flag = 0;
+ bool first = true;
+
+ foreach(AbstractInterface* iface, listInputs) {
+ if(iface->getPurpose() == AbstractInterface::Data) {
+ if (first) {
+ out << " -- input data ports" << endl;
+ first = false;
+ }
+ count--;
+ if (count == 0) flag = AbstractInterface::NoComma;
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ }
+ }
+ first = true;
+ foreach(AbstractInterface* iface, listInputs) {
+ if(iface->getPurpose() == AbstractInterface::Control) {
+ if (first) {
+ out << " -- input control ports" << endl;
+ first = false;
+ }
+ count--;
+ if (count == 0) flag = AbstractInterface::NoComma;
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ }
+ }
+ first = true;
+ foreach(AbstractInterface* iface, listOutputs) {
+ if(iface->getPurpose() == AbstractInterface::Data) {
+ if (first) {
+ out << " -- output data ports" << endl;
+ first = false;
+ }
+ count--;
+ if (count == 0) flag = AbstractInterface::NoComma;
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ }
+ }
+ first = true;
+ foreach(AbstractInterface* iface, listOutputs) {
+ if(iface->getPurpose() == AbstractInterface::Control) {
+ if (first) {
+ out << " -- output control ports" << endl;
+ first = false;
+ }
+ count--;
+ if (count == 0) flag = AbstractInterface::NoComma;
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ }
+ }
+ first = true;
+ foreach(AbstractInterface* iface, listBidirs) {
+ if(iface->getPurpose() == AbstractInterface::Data) {
+ if (first) {
+ out << " -- bidirs data ports" << endl;
+ first = false;
+ }
+ count--;
+ if (count == 0) flag = AbstractInterface::NoComma;
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;
+ }
+ }
+ out << " );" << endl << endl;
+ out << "end " << name << ";" << endl << endl;
+
+}
+
+void GroupBlock::generateArchitecture(QTextStream& out) throw(Exception) {
