#include "Exception.h"\r
class Exception;\r
\r
-\r
using namespace std;\r
using namespace Qt;\r
\r
void loadPatterns(QDomElement &root) throw(Exception);\r
bool checkPatterns(); \r
\r
-\r
+ inline void addSource(QString file) { sources.append(file); }\r
private: \r
QString xmlFile;\r
QString referenceXml;\r
QString referenceMd5;\r
- QString nameEnt, line;\r
+\r
+ QList<QString> sources;\r
+\r
QMap<QString, int> paramMap;\r
ArithmeticEvaluator* evaluator;\r
ReferenceBlock* reference;\r
--- /dev/null
+#include "ExternalSource.h"\r
+\r
+\r
+ExternalSource::ExternalSource(const QString& _name, const QString& _file, int _type) {\r
+\r
+ name = _name;\r
+ file = _file;\r
+ type = _type;\r
+}\r
--- /dev/null
+#ifndef __EXTERNALSOURCE_H__\r
+#define __EXTERNALSOURCE_H__\r
+\r
+#include <iostream>\r
+#include <fstream>\r
+\r
+#include <QtCore>\r
+\r
+\r
+using namespace std;\r
+using namespace Qt;\r
+\r
+class ExternalSource {\r
+\r
+public :\r
+\r
+ enum SourceType { Code = 1, Package, Netlist, InitFile};\r
+\r
+ ExternalSource(const QString& _name, const QString& _file, int _type = Code);\r
+\r
+ // getters\r
+ inline QString getName() { return name; }\r
+ inline QString getFile() { return file; }\r
+ inline int getType() { return type; }\r
+\r
+private:\r
+ QString name;\r
+ QString file;\r
+ int type;\r
+};\r
+\r
+#endif // __EXTERNALSOURCE_H__\r
+\r
try {
params->loadBlastConfiguration("blastconfig.xml");
+ // first load external sources
+ params->loadSources();
+
if (!QFileInfo::exists(params->refLib)) {
params->loadReferencesFromXml();
int ret = QMessageBox::question(this,tr("Building references library"),tr("The reference block library does not exists.\n References have been read directly from the xml descriptions of blocks.\n It can be saved into a library in order to start application faster. "), QMessageBox::Ok | QMessageBox::Cancel, QMessageBox::Ok);
implPathes.append(path);\r
cout << "impl path : " << qPrintable(path) << endl << endl;\r
}\r
+\r
+ QDomElement eltSource = eltImpl.nextSiblingElement("sources");\r
+ nbPathesStr = eltSource.attribute("nb","none");\r
+ nbPathes = nbPathesStr.toInt(&ok);\r
+ QDomNodeList listSourceDir = eltSource.elementsByTagName("source_lib");\r
+ if ((!ok) || (nbPathes != listSourceDir.size())) throw(Exception(CONFIGFILE_CORRUPTED));\r
+\r
+ for(int i=0;i<listSourceDir.size();i++) {\r
+ QDomNode nodeSourceDir = listSourceDir.at(i);\r
+ QDomElement eltSourceDir = nodeSourceDir.toElement();\r
+ if (eltSourceDir.isNull()) throw(Exception(CONFIGFILE_CORRUPTED));\r
+ QString path = eltSourceDir.attribute("path","none");\r
+ if (path == "none") throw(Exception(CONFIGFILE_CORRUPTED));\r
+ sourcePathes.append(path);\r
+ cout << "core path : " << qPrintable(path) << endl << endl;\r
+ }\r
+\r
// getting elt = the element <defaults>\r
// for each child element, initialize the associated attributes of Parameters\r
\r
- QDomElement eltDefaults = eltImpl.nextSiblingElement("defaults");\r
+ QDomElement eltDefaults = eltSource.nextSiblingElement("defaults");\r
\r
QDomElement eltBlocks = eltDefaults.firstChildElement("blocks");\r
QString attributeStr = eltBlocks.attribute("width", "none");\r
QString refXml = implRoot.attribute("ref_name","none");\r
QString refMd5 = implRoot.attribute("ref_md5","none");\r
BlockImplementation* impl = new BlockImplementation(fileName,refXml,refMd5);\r
+\r
+ QDomNodeList archNode = implRoot.elementsByTagName("architecture");\r
+\r
+ if (archNode.isEmpty()) {\r
+ cout << "impl has no architecture" << endl;\r
+ return;\r
+ }\r
+ QDomElement archElt = archNode.at(0).toElement();\r
+ QString compList = archElt.attribute("comp_list","none");\r
+ if (compList != "none") {\r
+ QStringList compos = compList.split(",");\r
+ foreach(QString s, compos) {\r
+ impl->addSource(s);\r
+ }\r
+ }\r
+\r
try {\r
impl->loadPatterns(implRoot);\r
}\r
libFile.close();\r
\r
}\r
+\r
+\r
+void Parameters::loadSources() throw(Exception) {\r
+\r
+ for(int i=0;i<sourcePathes.size();i++) {\r
+ cout << "analyzing " << qPrintable(sourcePathes.at(i)) << endl;\r
+ QDir dir(sourcePathes.at(i));\r
+ QStringList filter;\r
+ filter << "*.vhd";\r
+ dir.setNameFilters(filter);\r
+ QStringList list = dir.entryList();\r
+ for(int j=0;j<list.size();j++) {\r
+ QString fileName = dir.absolutePath();\r
+ fileName.append("/"+list.at(j));\r
+\r
+ cout << "parsing " << qPrintable(fileName) << " ... ";\r
+ QFile srcXML(fileName);\r
+ if (!srcXML.open(QIODevice::ReadOnly)) {\r
+ throw(Exception(IMPLFILE_NOACCESS));\r
+ }\r
+ QTextStream in(&srcXML);\r
+\r
+ QString line = in.readLine();\r
+ while (!line.isNull()) {\r
+ if (line.contains("package", Qt::CaseInsensitive)) {\r
+ QRegularExpression rxPack("^package (.+) is$",QRegularExpression::CaseInsensitiveOption);\r
+ QRegularExpressionMatch matchPack = rxPack.match(line);\r
+ if (matchPack.hasMatch()) {\r
+ QString packName = matchPack.captured(1);\r
+ cout << "found package " << qPrintable(packName) << endl;\r
+ availableSources.append(new ExternalSource(packName,fileName,ExternalSource::Package));\r
+ }\r
+ }\r
+ else if (line.contains("entity", Qt::CaseInsensitive)) {\r
+ QRegularExpression rxEnt("^entity (.+) is$",QRegularExpression::CaseInsensitiveOption);\r
+ QRegularExpressionMatch matchEnt = rxEnt.match(line);\r
+ if (matchEnt.hasMatch()) {\r
+ QString entityName = matchEnt.captured(1);\r
+ cout << "found entity " << qPrintable(entityName) << endl;\r
+ availableSources.append(new ExternalSource(entityName,fileName,ExternalSource::Code));\r
+ }\r
+ }\r
+ line = in.readLine();\r
+ }\r
+ srcXML.close();\r
+ cout << "OK" << endl;\r
+\r
+ }\r
+ }\r
+}\r
+\r
+ExternalSource* Parameters::searchSourceByName(const QString& name) {\r
+ foreach(ExternalSource* s, availableSources) {\r
+ if (s->getName() == name) return s;\r
+ }\r
+ return NULL;\r
+}\r
+\r
void Parameters::addAvailableBlock(ReferenceBlock *block) {\r
availableBlocks.append(block);\r
foreach (int id,block->getCategories()) {\r
class GroupWidget;\r
\r
#include "BlockImplementation.h"\r
+#include "ExternalSource.h"\r
\r
#include "Exception.h"\r
class Exception;\r
\r
// others\r
static QString normalizeName(const QString& name);\r
+ ExternalSource* searchSourceByName(const QString& name);\r
\r
/***************************************************\r
attributes that are general to the application\r
BlockLibraryTree* categoryTree;\r
QList<QString> refPathes;\r
QList<QString> implPathes;\r
+ QList<QString> sourcePathes;\r
QList<ReferenceBlock*> availableBlocks;\r
QList<BlockImplementation*> availableImplementations;\r
+ QList<ExternalSource*> availableSources;\r
+\r
ReferenceBlock* delayRef;\r
BlockImplementation* delayImpl; \r
\r
void loadImplementationsFromLib() throw(Exception);\r
void saveImplementationsToLib() throw(Exception);\r
\r
+ void loadSources() throw(Exception);\r
+\r
void addAvailableBlock(ReferenceBlock *block); \r
void parametersValidation();\r
void connectionsValidation();\r
using namespace std;
using namespace Qt;
-int main(int argc, char *argv[])
-{
+int main(int argc, char *argv[]) {
+
QApplication a(argc, argv);
MainWindow w;
w.show();
return a.exec();
-
}
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject>
-<!-- Written by QtCreator 4.2.0, 2018-03-21T17:45:46. -->
+<!-- Written by QtCreator 4.2.0, 2018-03-22T11:05:23. -->
<qtcreator>
<data>
<variable>EnvironmentId</variable>
- <value type="QByteArray">{3701e197-5b6c-48ea-9e98-a6cf6de18672}</value>
+ <value type="QByteArray">{94112477-caab-4897-8f75-5f412f2c883a}</value>
</data>
<data>
<variable>ProjectExplorer.Project.ActiveTarget</variable>
<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.0">
<value type="QString" key="language">Cpp</value>
<valuemap type="QVariantMap" key="value">
- <value type="QByteArray" key="CurrentPreferences">qt2</value>
+ <value type="QByteArray" key="CurrentPreferences">CppGlobal</value>
</valuemap>
</valuemap>
<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.1">
<value type="int" key="EditorConfiguration.CodeStyle.Count">2</value>
<value type="QByteArray" key="EditorConfiguration.Codec">UTF-8</value>
<value type="bool" key="EditorConfiguration.ConstrainTooltips">false</value>
- <value type="int" key="EditorConfiguration.IndentSize">2</value>
+ <value type="int" key="EditorConfiguration.IndentSize">4</value>
<value type="bool" key="EditorConfiguration.KeyboardTooltips">false</value>
<value type="int" key="EditorConfiguration.MarginColumn">80</value>
<value type="bool" key="EditorConfiguration.MouseHiding">true</value>
<value type="bool" key="EditorConfiguration.SmartSelectionChanging">true</value>
<value type="bool" key="EditorConfiguration.SpacesForTabs">true</value>
<value type="int" key="EditorConfiguration.TabKeyBehavior">0</value>
- <value type="int" key="EditorConfiguration.TabSize">4</value>
- <value type="bool" key="EditorConfiguration.UseGlobal">false</value>
+ <value type="int" key="EditorConfiguration.TabSize">8</value>
+ <value type="bool" key="EditorConfiguration.UseGlobal">true</value>
<value type="int" key="EditorConfiguration.Utf8BomBehavior">1</value>
<value type="bool" key="EditorConfiguration.addFinalNewLine">true</value>
<value type="bool" key="EditorConfiguration.cleanIndentation">true</value>
- <value type="bool" key="EditorConfiguration.cleanWhitespace">false</value>
+ <value type="bool" key="EditorConfiguration.cleanWhitespace">true</value>
<value type="bool" key="EditorConfiguration.inEntireDocument">false</value>
</valuemap>
</data>
<valuemap type="QVariantMap">
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Desktop</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Desktop</value>
- <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{ed04208c-8774-456b-99b9-4a02094ca7a4}</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{c934e180-ebc6-41ed-be82-502cc94f41f6}</value>
<value type="int" key="ProjectExplorer.Target.ActiveBuildConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveDeployConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveRunConfiguration">0</value>
<valuemap type="QVariantMap" key="ProjectExplorer.Target.RunConfiguration.0">
<value type="bool" key="Analyzer.QmlProfiler.AggregateTraces">false</value>
<value type="bool" key="Analyzer.QmlProfiler.FlushEnabled">false</value>
- <value type="uint" key="Analyzer.QmlProfiler.FlushInterval">0</value>
+ <value type="uint" key="Analyzer.QmlProfiler.FlushInterval">1000</value>
<value type="QString" key="Analyzer.QmlProfiler.LastTraceFile"></value>
<value type="bool" key="Analyzer.QmlProfiler.Settings.UseGlobalSettings">true</value>
<valuelist type="QVariantList" key="Analyzer.Valgrind.AddedSuppressionFiles"/>
<valuelist type="QVariantList" key="PE.EnvironmentAspect.Changes"/>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Arguments"></value>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Executable"></value>
- <value type="bool" key="ProjectExplorer.CustomExecutableRunConfiguration.UseTerminal">false</value>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.WorkingDirectory">%{buildDir}</value>
- <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Exécutable personnalisé</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Custom Executable</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.CustomExecutableRunConfiguration</value>
<value type="uint" key="RunConfiguration.QmlDebugServerPort">3768</value>
+ExternalSource.h
+ExternalSource.cpp
CustomDialog.h
CustomDialog.cpp
NewProjectDialog.h
<impl_lib path="/home/sdomas/Projet/Blast/code/blast/lib/implementations" />
</implementations>
+ <sources nb="1">
+ <source_lib path="/home/sdomas/Projet/Blast/code/blast/lib/sources" />
+ </sources>
+
<defaults>
<blocks width="175" height="125" font="Helvetica" font_size="14" />
<interfaces linelength="10" width="5" height="10" font="Helvetica" font_size="10" />
<xs:element ref="categories"/>
<xs:element ref="references"/>
<xs:element ref="implementations"/>
+ <xs:element ref="sources"/>
<xs:element ref="defaults" />
</xs:sequence>
</xs:group>
</xs:complexType>
</xs:element>
+ <xs:element name="source_lib">
+ <xs:complexType>
+ <xs:attribute ref="path" use="required"/>
+ </xs:complexType>
+ </xs:element>
+
<xs:element name="blocks">
<xs:complexType>
<xs:attributeGroup ref="blocksAttrGroup" />
</xs:complexType>
</xs:element>
+ <xs:element name="sources">
+ <xs:complexType >
+ <xs:sequence>
+ <xs:element ref="source_lib" maxOccurs="unbounded" />
+ </xs:sequence>
+ <xs:attribute ref="nb" use="required"/>
+ </xs:complexType>
+ </xs:element>
+
<xs:element name="defaults">
<xs:complexType>
<xs:group ref="defaultsElmtGroup" />
<xs:attribute name="value" type="xs:string" />
<xs:attribute name="pattern" type="xs:string"/>
<xs:attribute name="counter" type="xs:string"/>
+ <xs:attribute name="comp_list" type="xs:string"/>
+
<!-- déclaration des groupes d'éléments -->
<xs:attribute ref="use" />
</xs:complexType>
</xs:element>
-
- <xs:element name="architecture" type="xs:string" />
+
+ <xs:element name="architecture">
+ <xs:complexType>
+ <xs:simpleContent>
+ <xs:extension base="xs:string">
+ <xs:attribute ref="comp_list" />
+ </xs:extension>
+ </xs:simpleContent>
+ </xs:complexType>
+ </xs:element>
<xs:element name="patterns">
<xs:complexType>
<package name="numeric_std" use="all"/>
</library>
</libraries>
- <architecture>
+ <architecture comp_list="ram_dp_1024x8">
component ram_dp_1024x8
port (
clka : in std_logic;
<package name="numeric_std" use="all"/>
</library>
</libraries>
- <architecture>
+ <architecture comp_list="mult_accum">
component mult_accum
port (
@{clk} : in std_logic;
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2017 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file mult_accum.vhd when simulating
+-- the core, mult_accum. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY mult_accum IS
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sclr : IN STD_LOGIC;
+ bypass : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ s : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END mult_accum;
+
+ARCHITECTURE mult_accum_a OF mult_accum IS
+-- synthesis translate_off
+COMPONENT wrapped_mult_accum
+ PORT (
+ clk : IN STD_LOGIC;
+ ce : IN STD_LOGIC;
+ sclr : IN STD_LOGIC;
+ bypass : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+ s : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_mult_accum USE ENTITY XilinxCoreLib.xbip_multaccum_v2_0(behavioral)
+ GENERIC MAP (
+ c_a_type => 0,
+ c_a_width => 18,
+ c_accum_mode => 0,
+ c_accum_width => 48,
+ c_b_type => 0,
+ c_b_width => 18,
+ c_bypass_low => 0,
+ c_ce_overrides_sclr => 0,
+ c_has_bypass => 1,
+ c_latency => 1,
+ c_out_width => 48,
+ c_round_type => 0,
+ c_use_dsp48 => 1,
+ c_verbosity => 0,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_mult_accum
+ PORT MAP (
+ clk => clk,
+ ce => ce,
+ sclr => sclr,
+ bypass => bypass,
+ a => a,
+ b => b,
+ s => s
+ );
+-- synthesis translate_on
+
+END mult_accum_a;
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$07b
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--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2017 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram_dp_1024x8.vhd when simulating
+-- the core, ram_dp_1024x8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram_dp_1024x8 IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+ dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END ram_dp_1024x8;
+
+ARCHITECTURE ram_dp_1024x8_a OF ram_dp_1024x8 IS
+-- synthesis translate_off
+COMPONENT wrapped_ram_dp_1024x8
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+ dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_ram_dp_1024x8 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 10,
+ c_addrb_width => 10,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 0,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 2,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 1024,
+ c_read_depth_b => 1024,
+ c_read_width_a => 8,
+ c_read_width_b => 8,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 1,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 1024,
+ c_write_depth_b => 1024,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 8,
+ c_write_width_b => 8,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram_dp_1024x8
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ douta => douta,
+ clkb => clkb,
+ web => web,
+ addrb => addrb,
+ dinb => dinb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END ram_dp_1024x8_a;
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$0af
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used solely --
+-- for design, simulation, implementation and creation of design files --
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --
+-- devices or technologies is expressly prohibited and immediately --
+-- terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support appliances, --
+-- devices, or systems. Use in such applications are expressly --
+-- prohibited. --
+-- --
+-- (c) Copyright 1995-2017 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram_dp_2048x8.vhd when simulating
+-- the core, ram_dp_2048x8. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram_dp_2048x8 IS
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END ram_dp_2048x8;
+
+ARCHITECTURE ram_dp_2048x8_a OF ram_dp_2048x8 IS
+-- synthesis translate_off
+COMPONENT wrapped_ram_dp_2048x8
+ PORT (
+ clka : IN STD_LOGIC;
+ wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ clkb : IN STD_LOGIC;
+ web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+ dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+ );
+END COMPONENT;
+
+-- Configuration specification
+ FOR ALL : wrapped_ram_dp_2048x8 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
+ GENERIC MAP (
+ c_addra_width => 11,
+ c_addrb_width => 11,
+ c_algorithm => 1,
+ c_axi_id_width => 4,
+ c_axi_slave_type => 0,
+ c_axi_type => 1,
+ c_byte_size => 9,
+ c_common_clk => 1,
+ c_default_data => "0",
+ c_disable_warn_bhv_coll => 0,
+ c_disable_warn_bhv_range => 0,
+ c_enable_32bit_address => 0,
+ c_family => "spartan6",
+ c_has_axi_id => 0,
+ c_has_ena => 0,
+ c_has_enb => 0,
+ c_has_injecterr => 0,
+ c_has_mem_output_regs_a => 0,
+ c_has_mem_output_regs_b => 0,
+ c_has_mux_output_regs_a => 0,
+ c_has_mux_output_regs_b => 0,
+ c_has_regcea => 0,
+ c_has_regceb => 0,
+ c_has_rsta => 0,
+ c_has_rstb => 0,
+ c_has_softecc_input_regs_a => 0,
+ c_has_softecc_output_regs_b => 0,
+ c_init_file => "BlankString",
+ c_init_file_name => "no_coe_file_loaded",
+ c_inita_val => "0",
+ c_initb_val => "0",
+ c_interface_type => 0,
+ c_load_init_file => 0,
+ c_mem_type => 2,
+ c_mux_pipeline_stages => 0,
+ c_prim_type => 1,
+ c_read_depth_a => 2048,
+ c_read_depth_b => 2048,
+ c_read_width_a => 8,
+ c_read_width_b => 8,
+ c_rst_priority_a => "CE",
+ c_rst_priority_b => "CE",
+ c_rst_type => "SYNC",
+ c_rstram_a => 0,
+ c_rstram_b => 0,
+ c_sim_collision_check => "ALL",
+ c_use_bram_block => 0,
+ c_use_byte_wea => 0,
+ c_use_byte_web => 0,
+ c_use_default_data => 1,
+ c_use_ecc => 0,
+ c_use_softecc => 0,
+ c_wea_width => 1,
+ c_web_width => 1,
+ c_write_depth_a => 2048,
+ c_write_depth_b => 2048,
+ c_write_mode_a => "WRITE_FIRST",
+ c_write_mode_b => "WRITE_FIRST",
+ c_write_width_a => 8,
+ c_write_width_b => 8,
+ c_xdevicefamily => "spartan6"
+ );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram_dp_2048x8
+ PORT MAP (
+ clka => clka,
+ wea => wea,
+ addra => addra,
+ dina => dina,
+ douta => douta,
+ clkb => clkb,
+ web => web,
+ addrb => addrb,
+ dinb => dinb,
+ doutb => doutb
+ );
+-- synthesis translate_on
+
+END ram_dp_2048x8_a;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package tools_pkg is
+ type vector_of_std_logic_vector18 is array (natural range <>) of std_logic_vector(17 downto 0);
+ type vector_of_std_logic_vector8 is array (natural range <>) of std_logic_vector(7 downto 0);
+ type vector_of_std_logic is array (natural range <>) of std_logic;
+ type vector_of_unsigned8 is array (natural range <>) of unsigned(7 downto 0);
+ type vector_of_std_logic_vector4 is array (natural range <>) of std_logic_vector(3 downto 0);
+end tools_pkg;
$(BUILDPATH)/AbstractInputModifier.o \
$(BUILDPATH)/DelayInputModifier.o \
$(BUILDPATH)/BlockImplementation.o \
+ $(BUILDPATH)/ExternalSource.o \
$(BUILDPATH)/Graph.o \
$(BUILDPATH)/AbstractBoxItem.o \
$(BUILDPATH)/BoxItem.o \
