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finished testbench generation
[blast.git] / Dispatcher.cpp
2018-05-15 stephane Domasfinished testbench generation master
2018-05-09 stephane Domasfinalized analysis with clkconvert + started testbench...
2018-05-07 stephane Domasclkconvert OP compute done
2018-05-03 stephane Domasmoved clocks list to graph
2018-05-03 stephane Domaschanged sources to stimulis
2018-04-30 stephane Domasadded clk/rst link when creating a block
2018-04-27 stephane Domasadding link between ifaces and clk
2018-04-20 stephane Domasadded context to dispatcher op.
2018-04-06 stephane Domasfinished VHDL gen
2018-03-30 stephane Domasfinished VHDL gen. (but have to test further
2018-03-23 domas stephanestarted top group gen, added project subdirs
2018-03-22 stephane Domasmoved vhdl gen. into block
2018-01-24 stephane Domascorrect bug with clkrstgen
2018-01-24 stephane Domasadd clk/rst to groups
2018-01-14 stephane Domasadd graph modif, progress on vhdl generation
2017-12-08 stephane Domaschanges in output pattern comput
2017-05-23 stephane Domascorrected some warnings
2017-05-18 stephane Domasmodified pattern to use only QMap
2017-05-14 stephane Domaspattern comput done
2017-05-11 stephane Domasadded patterns and started OP computation
2017-05-10 stephane Domaschanged connection process
2017-05-10 stephane Domascorrect relative positionning of source/group
2017-05-09 stephane Domassource connection ok
2017-05-09 stephane Domasadded source items
2017-05-08 stephane Domasstart modifying read/write blocks and project to take...
2017-05-04 stephane Domasadding show/hide wb ifaces
2017-05-03 Stéphane Domasremoved leve attr. from interfaces
2017-05-03 stephane Domasloading project corrected
2017-04-27 stephane Domasinsert/move/remove block/groups/interface done. Next...
2017-04-26 Stéphane Domascorrecting bugs but still exsitings
2017-04-26 Stéphane Domas1st commit of all files