}\r
return lst;\r
}\r
+\r
QList<BlockParameter *> getWishboneParameters();\r
inline AbstractBlock* getParent() { return parent; }\r
inline bool getPatternComputed() { return patternComputed; }\r
+ inline int getTraversalLevel() { return traversalLevel; }\r
\r
// setters\r
void setName(const QString& str);\r
virtual void setParent(AbstractBlock* _parent);\r
inline void setPatternComputed(bool state) { patternComputed = state; }\r
+ inline void resetTraversalLevel() { traversalLevel = -1; }\r
+ inline void setTraversalLevel(int level) { traversalLevel = level; }\r
\r
// testers\r
virtual bool isReferenceBlock();\r
// patterns\r
virtual void checkInputPatternCompatibility() throw(Exception) = 0;\r
virtual void computeOutputPattern(int nbExec = -1) throw(Exception) = 0;\r
+ virtual void computeAdmittanceDelays() throw(Exception) = 0;\r
\r
protected:\r
\r
\r
// patterns \r
bool patternComputed;\r
+ int traversalLevel; // the level (0, 1, ...) during the traversal of the graph\r
\r
// NB: only GroupBlock and FunctionalBlock have a real parent, except sources that have no parents\r
AbstractBlock* parent;\r
--- /dev/null
+#include "AbstractInputModifier.h"\r
+\r
+AbstractInputModifier::AbstractInputModifier() {\r
+\r
+ pattern = new QList<char>();\r
+}\r
+\r
+AbstractInputModifier::~AbstractInputModifier() {\r
+\r
+ delete pattern;\r
+}\r
+\r
+bool AbstractInputModifier::isDelay() {\r
+ return false;\r
+}\r
+\r
+bool AbstractInputModifier::isComplexDelay() {\r
+ return false;\r
+}\r
+\r
+bool AbstractInputModifier::isFIFO() {\r
+ return false;\r
+}\r
+\r
+bool AbstractInputModifier::isDecimator() {\r
+ return false;\r
+}\r
+\r
--- /dev/null
+#ifndef __ABSTRACTINPUTMODIFIER_H__\r
+#define __ABSTRACTINPUTMODIFIER_H__\r
+\r
+#include <iostream>\r
+\r
+#include <QtCore>\r
+\r
+using namespace std;\r
+using namespace Qt;\r
+\r
+class AbstractInputModifier {\r
+\r
+public: \r
+ \r
+ AbstractInputModifier();\r
+ virtual ~AbstractInputModifier();\r
+\r
+ //getters\r
+ virtual QString getTypeStr() = 0;\r
+ virtual QString getParametersStr() = 0;\r
+\r
+ // setters\r
+\r
+ // testers\r
+ virtual bool isDelay();\r
+ virtual bool isComplexDelay();\r
+ virtual bool isFIFO();\r
+ virtual bool isDecimator();\r
+\r
+ // others\r
+ virtual QList<char>* getModifiedInput(QList<char>* input) = 0;\r
+\r
+ protected:\r
+ QList<char>* pattern; // the pattern modified by this\r
+};\r
+\r
+#endif // __ABSTRACTINPUTMODIFIER_H__\r
QString AbstractInterface::toVHDL(int context, int flags) throw(Exception) {
+
if (isReferenceInterface()) throw(Exception(IFACE_INVALID_TYPE));
QString msb = width;
QString ret="";
bool ok;
+ cout << "iface " << qPrintable(name) << " must be evaluated to vhdl :" << qPrintable(msb) << " with type = " << qPrintable(getTypeString()) << endl;
+
if ((context == BlockParameter::Entity) || (context == BlockParameter::Component)) {
QString formatBool = "%1 : %2 std_logic";
- QString formatVector = "%1 : %2 std_logic_vector(%3 downto %4)";
+ QString formatVector = "";
+ if (endianess == LittleEndian) formatVector = "%1 : %2 std_logic_vector(%3 downto %4)";
+ else formatVector = "%1 : %2 std_logic_vector(%4 to %3)";
+
if ((flags & BlockParameter::NoComma) == 0) {
formatBool.append(";");
formatVector.append(";");
orientation = "inout";
}
if (type == Boolean) {
- ret = formatVector.arg(name).arg(orientation);
+ ret = formatBool.arg(name).arg(orientation);
}
else if (type == Natural) {
int w = width.toInt(&ok);
}
}
else if (type == Expression) {
+
+
/* must check the following conditions :
- if it contains user/port parameters : must evaluate their numeric value
- if it contains generic parameters : just remove the $ -> the expression is not arithmetically evaluated.
QList<BlockParameter*> listPorts = owner->getPortParameters();
foreach(BlockParameter* p, listUsers) {
QString var = "$";
- var.append(p->getName());
+ var += p->getName();
if (width.contains(var)) {
int w = p->getValue().toInt(&ok);
if (!ok) throw(Exception(INVALID_VALUE));
}
foreach(BlockParameter* p, listPorts) {
QString var = "$";
- var.append(p->getName());
+ var += p->getName();
+ if (width.contains(var)) {
+ msb.replace(var,p->toVHDL(0,0));
+ }
+ }
+ foreach(BlockParameter* p, listGenerics) {
+ QString var = "$";
+ var += p->getName();
if (width.contains(var)) {
- BlockParameterPort* pp = (BlockParameterPort*)p;
- AbstractInterface* iface = owner->getIfaceFromName(pp->getIfaceName());
-
- int w = p->getValue().toInt(&ok);
- if (!ok) throw(Exception(INVALID_VALUE));
- msb.replace(var,p->getValue().toString());
+ msb.replace(var,p->getName());
}
}
-
- ret = formatVector.arg(name).arg(orientation).arg("toto").arg("0");
+ msb += "-1";
+ cout << "iface size :" << qPrintable(msb) << endl;
+ ret = formatVector.arg(name).arg(orientation).arg(msb).arg("0");
}
}
return ret;
}\r
\r
bool BlockImplementation::checkPatterns() {\r
- if (reference == NULL) return false;\r
+\r
+\r
+ if (reference == NULL) {\r
+ cout << "no ref. while checking patterns of implementation " << endl;\r
+ return false;\r
+ }\r
\r
AbstractInterface* iface; \r
QHashIterator<QString,QString> iterI(consumptionPattern);\r
while (iterI.hasNext()) {\r
iterI.next();\r
iface = reference->getIfaceFromName(iterI.key());\r
- if (iface == NULL) return false;\r
+ if (iface == NULL) {\r
+ cout << "cannot found an input ref. iface for impl. iface " << qPrintable(iterI.key()) << endl;\r
+ return false;\r
+ }\r
}\r
QHashIterator<QString,QString> iterO(productionPattern);\r
while (iterO.hasNext()) {\r
iterO.next();\r
iface = reference->getIfaceFromName(iterO.key());\r
- if (iface == NULL) return false;\r
+ if (iface == NULL) {\r
+ cout << "cannot found an output ref. iface for impl. iface " << qPrintable(iterI.key()) << endl;\r
+ return false;\r
+ }\r
} \r
return true; \r
}\r
for(int i = 0; i < listLib.length(); i++) {\r
QDomNode nodeLib = listLib.item(i);\r
QDomElement eltLib = nodeLib.toElement();\r
- QString nameLib = eltLib.attribute("name", "");\r
+ QString nameLib = eltLib.attribute("name","none");\r
out << "library " << nameLib << ";\n";\r
QDomNodeList listPack = eltLib.elementsByTagName("package");\r
for(int j = 0; j < listPack.length(); j++) {\r
QDomNode nodePack = listPack.item(j);\r
QDomElement eltPack = nodePack.toElement();\r
- QString namePack = eltPack.attribute("name", "");\r
- QString usePack = elt.attribute("use","");\r
- out << "use " << nameLib << "." << namePack << "." << usePack << ";\n";\r
+ QString namePack = eltPack.attribute("name","none");\r
+ QString usePack = eltPack.attribute("use","none");\r
+ out << "use " << nameLib << "." << namePack << "." << usePack << endl;\r
}\r
- out << "\n";\r
+ out << endl;\r
}\r
}\r
\r
void BlockImplementation::generateEntity(QTextStream& out, bool hasController) throw(Exception) {\r
\r
int i=0;\r
- nameEnt = reference->getName();\r
+ nameEnt = block->getName();\r
//QList<BlockParameter*> listParams = reference->getParameters();\r
- QList<AbstractInterface*> listInputs = reference->getInputs();\r
- QList<AbstractInterface*> listOutputs = reference->getOutputs();\r
- QList<AbstractInterface*> listBidirs = reference->getBidirs();\r
+ QList<AbstractInterface*> listInputs = block->getInputs();\r
+ QList<AbstractInterface*> listOutputs = block->getOutputs();\r
+ QList<AbstractInterface*> listBidirs = block->getBidirs();\r
QString typePort, namePort;\r
\r
out << "entity " << nameEnt << " is\n";\r
/* TODO : rewrite the generation to take into acocunt the new object hierarchy */\r
\r
// Generation of the generics\r
- QList<BlockParameter*> listGenerics = reference->getGenericParameters();\r
+ QList<BlockParameter*> listGenerics = block->getGenericParameters();\r
if ((!listGenerics.isEmpty()) || (hasController)) {\r
out << " generic (" << endl;\r
if (hasController) {\r
out << endl;\r
}\r
for(i=0;i<listGenerics.size()-1;i++) {\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0);\r
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma);\r
+ out << " " << listGenerics.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
\r
out << " );" << endl;\r
}\r
\r
// Generation of the clk & rst signals\r
out << " -- clk/rst" << endl;\r
- for(int i = 0; i < listInputs.size(); i++) {\r
- if(listInputs.at(i)->getPurpose() == AbstractInterface::Clock || listInputs.at(i)->getPurpose() == AbstractInterface::Reset) {\r
- out << " " << listInputs.at(i)->getName() << " : in std_logic;" << endl;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Clock || iface->getPurpose() == AbstractInterface::Reset) {\r
+ out << " " << iface->getName() << " : in std_logic;" << endl;\r
}\r
}\r
\r
out << " -- registers r/w via wishbone" << endl;\r
QList<BlockParameter*> listWB = reference->getWishboneParameters();\r
for(i=0;i<listWB.size()-1;i++) {\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0);\r
+ out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity, 0) << endl;\r
}\r
- out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma);\r
+ out << " " << listWB.at(i)->toVHDL(BlockParameter::Entity,BlockParameter::NoComma) << endl;\r
}\r
\r
\r
- // Generation of the data signals\r
- out << "-- data ports\n";\r
- for(int i = 0; i < listInputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listInputs.at(i)->getName()));\r
- if(listInputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listInputs.at(i)->getWidth());\r
- if(listInputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : in std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
+ int count = 0;\r
+ foreach(AbstractInterface* iface, block->getInterfaces()) {\r
+ if((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) count++;\r
}\r
+ // Generation of the data/control signals\r
\r
- for(int i = 0; i < listOutputs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listOutputs.at(i)->getName()));\r
- if(listOutputs.at(i)->getWidth().compare("1"))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth(listOutputs.at(i)->getWidth());\r
- if(listOutputs.at(i)->getPurpose() == 1)\r
- out << namePort << " : out std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
- }\r
+ int flag = 0;\r
+ bool first = true;\r
\r
- for(int i = 0; i < listBidirs.size(); i++) {\r
- namePort = getIfaceUserName(reference->AbstractBlock::getIfaceFromName(listBidirs.at(i)->getName()));\r
- if(listBidirs.at(i)->getWidth().compare(("1")))\r
- typePort = "std_logic";\r
- else\r
- typePort = calculateWidth((listBidirs.at(i)->getWidth()));\r
- if(listBidirs.at(i)->getPurpose() == 1)\r
- out << namePort << " : inout std_logic_vector(" << typePort << " -1 downto 0) ;\n";\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- input data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listInputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << " -- input control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- output data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listOutputs) {\r
+ if(iface->getPurpose() == AbstractInterface::Control) {\r
+ if (first) {\r
+ out << " -- output control ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
+ }\r
+ first = true;\r
+ foreach(AbstractInterface* iface, listBidirs) {\r
+ if(iface->getPurpose() == AbstractInterface::Data) {\r
+ if (first) {\r
+ out << " -- bidirs data ports" << endl;\r
+ first = false;\r
+ }\r
+ count--;\r
+ if (count == 0) flag = AbstractInterface::NoComma;\r
+ out << " " << iface->toVHDL(AbstractInterface::Entity, flag) << endl;\r
+ }\r
}\r
+ out << " );" << endl << endl;\r
+ out << "end " << nameEnt << ";" << endl << endl;\r
}\r
\r
// This function generates the architecture part of the VHDL document\r
void BlockImplementation::generateArchitecture(QDomElement &elt, QTextStream& out) throw(Exception) {\r
\r
QString expr;\r
- QDomElement eltArch = elt.nextSiblingElement("architecture");\r
- out << "architecture " << nameEnt <<"_1 of " << nameEnt << "is\n";\r
- QString implText = eltArch.text();\r
- QStringList listLine = implText.split("\n");\r
+ QString code = elt.text();\r
+ cout << qPrintable(code) << endl;\r
+ out << "architecture rtl of " << nameEnt << " is" << endl;\r
+\r
+ QStringList listLine = code.split("\n");\r
for(int i =0; i < listLine.size(); i++) {\r
- if(listLine.at(i).contains(QRegularExpression("@foreach{")) != -1) {\r
+ QString line = listLine.at(i).simplified();\r
+\r
+ /*\r
+ if(listLine.at(i).contains(QRegularExpression("@foreach{"))) {\r
while(listLine.at(i).compare("@endforeach") != -1) {\r
expr = expr + listLine.at(i) + '\n';\r
i++;\r
expr = expr + listLine.at(i);\r
out << evalComplex(expr, 1) << '\n';\r
}\r
- if(listLine.at(i).contains(QRegularExpression("@caseeach{")) != -1) {\r
+ if(listLine.at(i).contains(QRegularExpression("@caseeach{"))) {\r
while(listLine.at(i).compare("@endcaseeach") != -1) {\r
expr = expr + listLine.at(i) + '\n';\r
i++;\r
expr = expr + listLine.at(i);\r
out << evalComplex(expr, 2) << '\n';\r
}\r
-\r
- if(listLine.at(i).contains('@') == -1)\r
- out << listLine.at(i) << "\n";\r
- else\r
- out << eval(listLine.at(i), out) << "\n";\r
+*/\r
+ if(line.contains("@{")) {\r
+ out << line << endl;\r
+ }\r
}\r
}\r
\r
inline QHash<QString,QString> getProductionPattern() { return productionPattern; }\r
inline QString getProductionCounter() { return productionCounter; }\r
// setters\r
+ inline void setDelta(QString _delta) { delta = _delta; }\r
+ inline void setConsumptionPattern(QHash<QString,QString> pattern) { consumptionPattern = pattern; }\r
+ inline void setProductionPattern(QHash<QString,QString> pattern) { productionPattern = pattern; }\r
+ inline void setProductionCounter(QString pattern) { productionCounter = pattern; }\r
\r
QString eval(QString line, QTextStream& out);\r
QString evalComplex(QString line, int num);\r
#include "BlockLibraryTree.h"
-BlockLibraryTree::BlockLibraryTree() {
- tabCategories = NULL;
- tabIdParent = NULL;
+BlockLibraryTree::BlockLibraryTree() {
nbCategories = 0;
}
for(int i=0;i<nbCategories;i++) {
delete tabCategories[i];
- }
- delete [] tabCategories;
+ }
nbCategories = 0;
}
tabCategories[i]->blocks.clear();
}
}
-
+/*
void BlockLibraryTree::addItem(QXmlAttributes &attributes)
{
nbCategories++;
tabCategories[id] = cat;
tabIdParent[id] = idParent;
}
-
-bool BlockLibraryTree::initChildParent()
-{
+*/
+bool BlockLibraryTree::initChildParent() {
// initializing parent/childs
+ bool ok;
for(int i=0;i<nbCategories;i++) {
- if (tabIdParent[i] != -1) {
- if (tabIdParent[i] >= nbCategories) return false;
- tabCategories[i]->setParent(tabCategories[tabIdParent[i]]);
- tabCategories[tabIdParent[i]]->addChild(tabCategories[i]);
+ if (tabIdParent[i] >= 0) {
+ ok = false;
+ foreach (BlockCategory* cat, tabCategories) {
+ if (cat->getId() == tabIdParent[i]) {
+ tabCategories[i]->setParent(cat);
+ cat->addChild(tabCategories[i]);
+ ok = true;
+ break;
+ }
+ }
+ if (!ok) return false;
}
}
return true;
if (elt.tagName() != "categories") throw(Exception(CONFIGFILE_CORRUPTED));
- QString nbStr = elt.attribute("nb","none");
bool ok;
- int nb = nbStr.toInt(&ok);
QDomNodeList list = elt.elementsByTagName("category");
nbCategories = list.size();
- if (nb != nbCategories) throw(Exception(CONFIGFILE_CORRUPTED));
QString name;
int id;
QString idStr;
int idParent;
QString idParentStr;
- tabCategories = new BlockCategory* [nbCategories];
- tabIdParent = new int[nbCategories];
BlockCategory* cat = NULL;
// creating all BlockCategory objects
idStr = e.attribute("id","none");
idParentStr = e.attribute("parent","none");
id = idStr.toInt(&ok);
- if ((!ok) || (id < 0) || (id >= nbCategories)) throw(Exception(CONFIGFILE_CORRUPTED));
+ if ((!ok) || (id < 0) || (id >= 100)) throw(Exception(CONFIGFILE_CORRUPTED));
idParent = idParentStr.toInt(&ok);
- if ((!ok)|| (idParent < -1) || (idParent >= nbCategories)) throw(Exception(CONFIGFILE_CORRUPTED));
+ if ((!ok)|| (idParent < -1) || (idParent >= 100)) throw(Exception(CONFIGFILE_CORRUPTED));
cat = new BlockCategory(name,id);
- tabCategories[id] = cat;
- tabIdParent[id] = idParent;
+ tabCategories.append(cat);
+ tabIdParent.append(idParent);
}
+ cat = new BlockCategory("hidden",100);
+ tabCategories.append(cat);
+ tabIdParent.append(0);
ok = initChildParent();
- delete [] tabIdParent;
+
if (!ok) throw(Exception(CONFIGFILE_CORRUPTED));
}
BlockCategory* BlockLibraryTree::searchCategory(int id) {
- if (tabCategories != NULL) {
- if ((id>=0) && (id < nbCategories)) {
- return tabCategories[id];
- }
+ foreach(BlockCategory* cat, tabCategories) {
+ if (cat->getId() == id) return cat;
}
-
return NULL;
}
BlockCategory *BlockLibraryTree::getRoot() {
- if (tabCategories != NULL) {
- if (nbCategories > 0) {
- return tabCategories[0];
- }
- }
- return NULL;
+
+ return searchCategory(0);
}
The root of the tree is in fact tabCategories[0]
*/
- BlockCategory** tabCategories;
- int* tabIdParent;
+ QList<BlockCategory*> tabCategories;
+ QList<int> tabIdParent;
int nbCategories;
};
QList<BlockCategory *> childs = catParent->getAllChilds();
foreach(BlockCategory* cat, childs){
- newItemCat = new QTreeWidgetItem(itemParent);
- newItemCat->setData(0,Qt::DisplayRole, cat->getName());
- QList<ReferenceBlock*> list = cat->getBlocks();
- for(int i=0; i<list.length(); i++){
- newItemBlock = new QTreeWidgetItem(newItemCat);
- newItemBlock->setData(0,Qt::DisplayRole, list.at(i)->getName());
- newItemBlock->setData(1,Qt::DisplayRole, cat->getId());
- newItemBlock->setData(2,Qt::DisplayRole, i);
- newItemBlock->setIcon(0,QIcon("icons/window_new.png"));
+
+ if (cat->getId()<100) {
+ newItemCat = new QTreeWidgetItem(itemParent);
+ newItemCat->setData(0,Qt::DisplayRole, cat->getName());
+ QList<ReferenceBlock*> list = cat->getBlocks();
+ for(int i=0; i<list.length(); i++){
+ newItemBlock = new QTreeWidgetItem(newItemCat);
+ newItemBlock->setData(0,Qt::DisplayRole, list.at(i)->getName());
+ newItemBlock->setData(1,Qt::DisplayRole, cat->getId());
+ newItemBlock->setData(2,Qt::DisplayRole, i);
+ newItemBlock->setIcon(0,QIcon("icons/window_new.png"));
+ }
+ addChild(cat,newItemCat);
}
- addChild(cat,newItemCat);
}
/* TO DO :
- getting the childs of catParent
\r
double BlockParameter::getDoubleValue(bool* ok) {\r
if ((type == Real) || (type == Natural) || (type == Positive) || (type == Integer)) {\r
- *ok = true;\r
+ *ok = true; \r
return getValue().toDouble();\r
}\r
*ok = false;\r
virtual QVariant getValue(); // may be overriden\r
int getIntValue(bool* ok);\r
double getDoubleValue(bool* ok);\r
- bool getBooleanValue(bool* ok); \r
+ bool getBooleanValue(bool* ok);\r
QString getStringValue();\r
virtual QString getContext() = 0;\r
\r
}\r
\r
if (!userValue.isNull()) {\r
- ret = formatValue.arg(name).arg(type).arg(userValue.toString());\r
+ ret = formatValue.arg(name).arg(getTypeString()).arg(userValue.toString());\r
}\r
else if (!defaultValue.isNull()) {\r
- ret = formatValue.arg(name).arg(type).arg(defaultValue.toString());\r
+ ret = formatValue.arg(name).arg(getTypeString()).arg(defaultValue.toString());\r
}\r
else {\r
- ret = formatNoValue.arg(name).arg(type);\r
+ ret = formatNoValue.arg(name).arg(getTypeString());\r
}\r
}\r
else if (context == BlockParameter::Architecture) {\r
QAction* showWishboneIface = NULL;
QAction* showParameters = NULL;
QAction* showPatterns = NULL;
+ QAction* showModifier = NULL;
+ QAction* removeModifier = NULL;
+ QAction* generateVHDL = NULL;
InterfaceItem* ifaceItem = getInterfaceItemFromCursor(event->pos().x(), event->pos().y());
// menu for interface
}
}
}
- if ((iface->getAssociatedIface() != NULL) && (iface->getDirection() == AbstractInterface::Output)) {
- showPatterns = menu.addAction("Show patterns");
+ if (iface->getAssociatedIface() != NULL) {
+ if (iface->getDirection() == AbstractInterface::Output) {
+ showPatterns = menu.addAction("Show output pattern");
+ }
+ else if (iface->getDirection() == AbstractInterface::Input) {
+ showPatterns = menu.addAction("Show input pattern");
+ }
+ }
+
+ if (iface->getInputModifier() != NULL) {
+ removeModifier = menu.addAction("Remove input modifier");
+ }
+ if (iface->getInputModifier() != NULL) {
+ showModifier = menu.addAction("Show input modifier parameters");
}
+
}
// menu for blocks (group or func)
else {
showWishboneIface->setChecked(wishboneVisible);
}
removeAction = menu.addAction("Remove");
+ generateVHDL = menu.addAction("Generate VHDL");
}
QAction* selectedAction = NULL;
else if(selectedAction == showPatterns) {
dispatcher->showPatterns(ifaceItem);
}
+ else if(selectedAction == removeModifier) {
+ dispatcher->removeModifier(ifaceItem);
+ }
+ else if(selectedAction == showModifier) {
+ dispatcher->showModifier(ifaceItem);
+ }
+ else if(selectedAction == generateVHDL) {
+ dispatcher->generateBlockVHDL(this);
+ }
+
}
void BoxItem::loadFunctional(QDomElement funcElement) throw(Exception) {
*/
functionalBlock->setName(name);
setRefBlock(functionalBlock);
+ params->blockToItem.insert(functionalBlock,this);
setPos(posX,posY);
setDimension(dimX,dimY);
ConnectedInterface::ConnectedInterface(AbstractBlock* _owner) : AbstractInterface(_owner) {\r
connectedFrom = NULL;\r
outputPattern = NULL;\r
+ inputModifier = NULL;\r
\r
}\r
\r
ConnectedInterface::ConnectedInterface(AbstractBlock* _owner, const QString& _name, int _direction, int _purpose, const QString& _type, const QString& _width) : AbstractInterface(_owner, _name, _direction, _purpose, _type, _width) {\r
- connectedFrom = NULL;\r
+ connectedFrom = NULL; \r
outputPattern = NULL;\r
+ inputModifier = NULL;\r
}\r
\r
-ConnectedInterface::~ConnectedInterface() {\r
+ConnectedInterface::~ConnectedInterface() { \r
if (outputPattern != NULL) delete outputPattern;\r
}\r
\r
if (outputPattern != NULL) delete outputPattern;\r
outputPattern = pattern; \r
}\r
+\r
void ConnectedInterface::connectTo(ConnectedInterface *iface) {\r
\r
connectedTo.append(iface);\r
}\r
return NULL;\r
}\r
+\r
+void ConnectedInterface::clearInputModifier() {\r
+ if (inputModifier != NULL) delete inputModifier;\r
+ inputModifier = NULL;\r
+}\r
#include "AbstractInterface.h"
class ReferenceInterface;
+#include "AbstractInputModifier.h"
+
#include "Exception.h"
// getters
inline QList<ConnectedInterface*> getConnectedTo() { return connectedTo;}
- inline ConnectedInterface* getConnectedFrom() { return connectedFrom;}
- inline QList<char>* getOutputPattern() { return outputPattern; }
+ inline ConnectedInterface* getConnectedFrom() { return connectedFrom;}
+ inline QList<char>* getOutputPattern() { return outputPattern; }
+ inline AbstractInputModifier* getInputModifier() { return inputModifier; }
- // setters
+ // setters
void setOutputPattern(QList<char>* pattern);
+ inline void setInputModifier(AbstractInputModifier* mod) { inputModifier = mod; }
// testers
inline bool isConnectedTo(){return connectedTo.length() != 0;}
+ inline bool isConnectedToMany(){return connectedTo.length()>=2;}
inline bool isConnectedFrom(){return connectedFrom != NULL;}
virtual bool canConnectTo(AbstractInterface* iface) = 0;
virtual bool canConnectFrom(AbstractInterface* iface) = 0;
//bool connectFrom(ConnectedInterface* iface);
ConnectedInterface* getConnectionToParentGroup();
ConnectedInterface* getConnectionFromParentGroup();
+ void clearInputModifier();
virtual AbstractInterface *clone() = 0;
//void removeConnectedTo(ConnectedInterface *inter);
* this interface. connecteFrom references such an interface if it exists.
*/
ConnectedInterface* connectedFrom;
-
- // patterns
+ AbstractInputModifier* inputModifier; // if needed, represent a block taht does not appear on screen but taht will modify the stream.
+
+ // patterns
QList<char>* outputPattern; //! only usefull for output interfaces
};
/* have to check if the connection can be removed.
If the from or to InterfaceItem is owned by a group item, and this item
is both connected to and from, thus it is impossible to remove this connection
+ because there would be a group interface alone and not connected and this situation is not allowed.
+
+ Nevertheless, there are 2 exceptions :
+ - a from group interface is connected to more than one input interface
+ - the connection is between a source block outside the top group and the top group
*/
bool canRemove = true;
- InterfaceItem* groupIfaceItem = NULL;
+
if (fromInterfaceItem->getOwner()->isGroupItem()) {
- groupIfaceItem = fromInterfaceItem;
- }
- else if (toInterfaceItem->getOwner()->isGroupItem()) {
- groupIfaceItem = toInterfaceItem;
+ ConnectedInterface* ref = fromInterfaceItem->refInter;
+ if ((ref->isConnectedFrom()) && (ref->getConnectedTo().length() == 1)) {
+ canRemove = false;
+ }
}
-
- if (groupIfaceItem != NULL) {
- ConnectedInterface* ref = groupIfaceItem->refInter;
+ else if ((toInterfaceItem->getOwner()->isGroupItem()) && (! toInterfaceItem->getOwner()->getRefBlock()->isTopGroupBlock())) {
+ ConnectedInterface* ref = toInterfaceItem->refInter;
if ((ref->isConnectedFrom()) && (ref->isConnectedTo())) {
canRemove = false;
}
--- /dev/null
+#include "DelayInputModifier.h"\r
+\r
+DelayInputModifier::DelayInputModifier(int _delayLength) : AbstractInputModifier() {\r
+ setDelayLength(_delayLength);\r
+}\r
+\r
+void DelayInputModifier::setDelayLength(int _delayLength) {\r
+ if (_delayLength < 1) _delayLength = 1;\r
+ delayLength = _delayLength;\r
+}\r
+\r
+QList<char>* DelayInputModifier::getModifiedInput(QList<char>* input) {\r
+\r
+ pattern->clear();\r
+ for(int i=0;i<delayLength;i++) pattern->append(0);\r
+ pattern->append(*input);\r
+ return pattern;\r
+}\r
+\r
+QString DelayInputModifier::getTypeStr() {\r
+ return "delay";\r
+}\r
+\r
+QString DelayInputModifier::getParametersStr() {\r
+ return QString::number(delayLength);\r
+}\r
+\r
+bool DelayInputModifier::isDelay() {\r
+ return true;\r
+}\r
--- /dev/null
+#ifndef __DELAYINPUTMODIFIER_H__\r
+#define __DELAYINPUTMODIFIER_H__\r
+\r
+#include <iostream>\r
+#include <QtCore>\r
+\r
+#include "AbstractInputModifier.h"\r
+using namespace std;\r
+using namespace Qt;\r
+\r
+class DelayInputModifier : public AbstractInputModifier {\r
+\r
+public: \r
+ \r
+ DelayInputModifier(int _delayLength = 1);\r
+ // getters\r
+ inline int getDelayLength() { return delayLength; }\r
+ // setters\r
+ void setDelayLength(int _delayLength);\r
+ // testers\r
+ bool isDelay();\r
+\r
+ // others\r
+ QList<char>* getModifiedInput(QList<char>* input);\r
+\r
+ QString getTypeStr();\r
+ QString getParametersStr();\r
+\r
+private:\r
+ int delayLength;\r
+};\r
+\r
+#endif // __DELAYINPUTMODIFIER_H__\r
#include "BlockLibraryWidget.h"
#include "BlockLibraryTree.h"
+#include "AbstractInputModifier.h"
+#include "DelayInputModifier.h"
+
+
#include "InterfacePropertiesWindow.h"
int Dispatcher::sceneCounter = 0;
*/
}
+void Dispatcher::generateBlockVHDL(BoxItem *item){
+ static QString fctName = "Dispatcher::generateBlockVHDL()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+
+ if (item->getRefBlock()->isFunctionalBlock()) {
+ FunctionalBlock* block = AB_TO_FUN(item->getRefBlock());
+ ReferenceBlock* ref = block->getReference();
+ BlockImplementation* impl = ref->getImplementations().at(0);
+ try {
+ impl->generateVHDL(block,"/home/sdomas/");
+ }
+ catch(Exception e) {
+ cout << qPrintable(e.getMessage()) << endl;
+ }
+ }
+}
+
void Dispatcher::renameFunctionalBlock(BoxItem *item){
static QString fctName = "Dispatcher::renameFunctionalBlock()";
#ifdef DEBUG_FCTNAME
#ifdef DEBUG_FCTNAME
cout << "call to " << qPrintable(fctName) << endl;
#endif
- ConnectedInterface* iface = AI_TO_CON(item->refInter->getAssociatedIface());
- foreach(char c, *(iface->getOutputPattern())) {
- cout << (int)c;
+ QString msg = "";
+ if (item->refInter->getDirection() == AbstractInterface::Input) {
+ msg = "Input pattern of iface ";
+ msg += item->refInter->getName();
+ msg += " owned by ";
+ msg += item->refInter->getOwner()->getName();
+ msg += " is:\n";
+ ConnectedInterface* iface = AI_TO_CON(item->refInter->getAssociatedIface());
+ ConnectedInterface* fromIface = iface->getConnectedFrom();
+ if (fromIface->getOutputPattern() == NULL) return;
+ foreach(char c, *(fromIface->getOutputPattern())) {
+ msg += QString::number((int)c);
+ }
+ msg += "\n";
+ }
+ else if (item->refInter->getDirection() == AbstractInterface::Output) {
+ msg = "Output pattern of iface ";
+ msg += item->refInter->getName();
+ msg += " owned by ";
+ msg += item->refInter->getOwner()->getName();
+ msg += " is:\n";
+ ConnectedInterface* iface = AI_TO_CON(item->refInter->getAssociatedIface());
+ if (iface->getOutputPattern() == NULL) return;
+ foreach(char c, *(iface->getOutputPattern())) {
+ msg += QString::number((int)c);
+ }
+ msg += "\n";
+ }
+ QMessageBox::information(NULL,"Interface pattern",msg,QMessageBox::Ok,QMessageBox::Ok);
+}
+
+void Dispatcher::showModifier(InterfaceItem *item) {
+ static QString fctName = "Dispatcher::showModifier()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+ QString msg = "";
+ AbstractInputModifier* mod = item->refInter->getInputModifier();
+ if (mod->isDelay()) {
+ DelayInputModifier* delay = (DelayInputModifier *)mod;
+ msg = "Pattern of iface ";
+ msg += item->refInter->getName();
+ msg += " owned by ";
+ msg += item->refInter->getOwner()->getName();
+ msg += " is modified by a simple delay of ";
+ msg += QString::number(delay->getDelayLength());
+
}
- cout << endl;
+ QMessageBox::information(NULL,"Interface pattern",msg,QMessageBox::Ok,QMessageBox::Ok);
}
+void Dispatcher::removeModifier(InterfaceItem *item) {
+ static QString fctName = "Dispatcher::showModifier()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+
+ item->refInter->clearInputModifier();
+}
+
+
void Dispatcher::duplicateBoxItem(BoxItem *item){
static QString fctName = "Dispatcher::duplicateBoxItem()";
#ifdef DEBUG_FCTNAME
}
-void Dispatcher::addBlock(int idCategory, int idBlock, int idScene) {
+BoxItem* Dispatcher::addBlock(int idCategory, int idBlock, int idScene) {
static QString fctName = "Dispatcher::addBlock()";
#ifdef DEBUG_FCTNAME
cout << "call to " << qPrintable(fctName) << endl;
#endif
bool newSource = false;
+ BoxItem* item = NULL;
GroupScene *scene = getSceneById(idScene);
ReferenceBlock* ref = params->getReferenceBlock(idCategory,idBlock);
// if block has no inputs, propose to add it as a source to top scene
else {
GroupBlock* group = AB_TO_GRP(scene->getGroupItem()->getRefBlock());
FunctionalBlock* newOne = params->getGraph()->createFunctionalBlock(group, ref);
- scene->createBoxItem(newOne);
+ item = scene->createBoxItem(newOne);
+ params->blockToItem.insert(newOne,item);
}
params->unsaveModif = true;
+ return item;
}
// creating the view part of the group
GroupItem *group = new GroupItem(NULL,refBlock,this,params);
+
// adding the fake interface to the top group item
//InterfaceItem* item = new InterfaceItem(0.0 , Parameters::West, (ConnectedInterface*)iface, group, params);
//group->addInterface(item,true);
GroupBlock* groupBlock = AB_TO_GRP(upperItemOfGroupItem->getRefBlock());
// creating the view part of the group
GroupItem *groupItem = new GroupItem(upperItemOfGroupItem,groupBlock,this,params);
+
// creating the group widget
group = new GroupWidget(parentWidget, this, params);
// getting the newly created scene
FunctionalBlock* block = AB_TO_FUN(item->getRefBlock());
item->getScene()->removeBoxItem(item);
params->getGraph()->removeFunctionalBlock(block);
+ params->blockToItem.remove(block);
+
}
else if (item->getRefBlock()->isGroupBlock()) {
return NULL;
}
+void Dispatcher::findGraphModifications(FunctionalBlock *block) {
+ static QString fctName = "Dispatcher::findGraphModifications()";
+#ifdef DEBUG_FCTNAME
+ cout << "call to " << qPrintable(fctName) << endl;
+#endif
+
+ block->computeAdmittanceDelays();
+ // get the block item that is associated to block
+ BoxItem* toBlockItem = params->blockToItem.value(block);
+
+ /* VERSION 1: just add delays if needed */
+ QMap<AbstractInterface*,QList<int>* > delays = block->getAdmittanceDelays();
+ QMapIterator<AbstractInterface*,QList<int>* > iterD(delays);
+ while (iterD.hasNext()) {
+ iterD.next();
+ QList<int>* delay = iterD.value();
+ if (delay->at(0) > 0) {
+ // create delay and associate it to the connected input
+ AbstractInputModifier* mod = new DelayInputModifier(delay->at(0));
+ ConnectedInterface* toIface = AI_TO_CON(iterD.key()->getAssociatedIface());
+ cout << "modify input of " << qPrintable(toIface->getName()) << endl;
+ toIface->setInputModifier(mod);
+ // repaint
+ toBlockItem->update();
+ }
+ }
+}
+
BoxItem* getBoxItemById(int id);
GroupItem* getGroupItemById(int id);
InterfaceItem* getInterfaceItemById(int id);
-
+
// block ops
- void addBlock(int idCategory, int idBlock, int idScene);
+ BoxItem* addBlock(int idCategory, int idBlock, int idScene);
void removeBoxItem(BoxItem* item);
void duplicateBoxItem(BoxItem* item);
void renameFunctionalBlock(BoxItem* item);
+ void generateBlockVHDL(BoxItem* item);
void renameGroupBlock(GroupItem* item);
void renameSourceBlock(SourceItem* item);
void removeSourceItem(SourceItem* item);
void duplicateSourceItem(SourceItem* item);
+
// interface ops
/*!
* \brief connectInterToGroup
void showProperties(InterfaceItem *inter);
void renameInterface(InterfaceItem* item);
void showPatterns(InterfaceItem* item);
+ void showModifier(InterfaceItem* item);
+ void removeModifier(InterfaceItem* item);
// connection ops
bool createConnection(InterfaceItem *iface1, InterfaceItem *iface2);
void removeConnection(ConnectionItem *conn);
+ // analysis ops
+ void findGraphModifications(FunctionalBlock* block); // find modif so that block has compatible inputs
+
// others
void showBlocksLibrary();
#include "Exception.h"
-Exception::Exception(int _id) {
+Exception::Exception(int _id, void *_source) {
id = _id;
message = getDefaultMessage();
+ source = _source;
}
Exception::Exception(const Exception& other) {
id = other.id;
message = other.message;
+ source = other.source;
}
QString Exception::getDefaultMessage() {
case IP_AP_NOTCOMPAT : ret = tr("IP and AP not compatible"); break;
case IP_END_NULLCOL : ret = tr("IP ends with anull column (normally not possible during compat. check)"); break;
case AP_TOO_SHORT : ret = tr("AP has been badly computed, leading to a AP shorter than needed (NB: it is an abnormal case)"); break;
+ case IFACE_NOT_CONNECTED : ret = tr("an interface with control is not coonected, leading to an impossible graph analysis"); break;
}
return ret;
// exception for patterns
#define INVALID_REFBLOCK_USE 10001
-#define INVALID_DELTA_CP 10002 // delta and CP are not consistent (NB: used during admittance computation)
+#define INVALID_GROUPBLOCK_USE 10002
+#define INVALID_DELTA_CP 10003 // delta and CP are not consistent (NB: used during admittance computation)
#define EVAL_PARAM_UNKNOWN 10101 // a variable used in an expression is not defined as a block parameter
#define EVAL_PARAM_NOVALUE 10102 // can't get the double value of a block parameter
#define IP_END_NULLCOL 10503 // IP ends with anull column (normally not possible during compat. check)
#define AP_TOO_SHORT 10504 // AP has been badly computed, leading to a AP shorter than needed (NB: it is an abnormal case)
+#define IFACE_NOT_CONNECTED 10601 // an interface with control is not connected => impossible to analyz the graph
using namespace std;
using namespace Qt;
public:
- Exception(int _id);
+ Exception(int _id, void* _source = NULL);
Exception(const Exception& other);
inline int getType() { return id; }
inline void setMessage(QString _message) { message = _message; }
inline QString getMessage() { return message; }
QString getDefaultMessage();
+ inline void* getSource() { return source; }
private:
int id;
QString message;
+ void* source;
};
cout << "call to " << qPrintable(fctName) << endl;\r
#endif\r
\r
+ // first clear if already exists\r
+ clearConsumptionPattern();\r
+\r
lengthCP = -1; \r
QHash<QString,QString> consPattern = implementation->getConsumptionPattern(); \r
\r
FunctionalInterface* connIface = AI_TO_FUN(iface);\r
QString refName = connIface->getReference()->getName(); \r
if (! consPattern.contains(refName)) {\r
- throw(Exception(NO_IFACE_CP));\r
+ throw(Exception(NO_IFACE_CP,this));\r
cerr << "no consumption pattern for reference interface " << qPrintable(refName) << endl;\r
}\r
QList<char>* pattern = NULL;\r
}\r
else {\r
if (pattern->size() != lengthCP) {\r
- throw(Exception(INVALID_IFACE_CP_LENGTH));\r
+ throw(Exception(INVALID_IFACE_CP_LENGTH,this));\r
}\r
}\r
} \r
#ifdef DEBUG_FCTNAME\r
cout << "call to " << qPrintable(fctName) << endl;\r
#endif\r
+\r
+ // first clear if already exists\r
+ clearProductionPattern();\r
\r
lengthPP = -1; \r
QHash<QString,QString> prodPattern = implementation->getProductionPattern(); \r
FunctionalInterface* connIface = AI_TO_FUN(iface);\r
QString refName = connIface->getReference()->getName(); \r
if (! prodPattern.contains(refName)) {\r
- throw(Exception(NO_IFACE_PP)); \r
+ throw(Exception(NO_IFACE_PP,this));\r
}\r
QList<char>* pattern = NULL;\r
try {\r
}\r
else {\r
if (pattern->size() != lengthPP) {\r
- throw(Exception(INVALID_IFACE_PP_LENGTH));\r
+ throw(Exception(INVALID_IFACE_PP_LENGTH,this));\r
}\r
}\r
} \r
#ifdef DEBUG_FCTNAME\r
cout << "call to " << qPrintable(fctName) << endl;\r
#endif\r
+\r
+ // first clear if already exists\r
+ productionCounter.clear();\r
+\r
\r
QStringList counterParts = implementation->getProductionCounter().split(",");\r
foreach(QString s, counterParts) {\r
s.chop(1);\r
QStringList gen = s.split(":");\r
if (gen.size() != 3) {\r
- throw(Exception(INVALID_IFACE_PC));\r
+ throw(Exception(INVALID_IFACE_PC,this));\r
}\r
int start = 0;\r
int nb = 0;\r
#ifdef DEBUG_FCTNAME\r
cout << "call to " << qPrintable(fctName) << endl;\r
#endif\r
- \r
- QList<char> lst;\r
- QString p = patternIn;\r
+ /* expanding a pattern is done in two steps :\r
+ - 1 : finding all variables that correspond to an expression\r
+ and copy them in the pattern\r
+ - 2 : parsing the result\r
+\r
+ Note that the result MUST contain only variables that have a\r
+ integer/double value. Otherwise, expanding will fail.\r
+\r
+ */\r
+\r
+ // first step.\r
+\r
+ QString p = replaceExpressions(patternIn);\r
+\r
+ QList<char> lst; \r
p.append(')');\r
int offset = 0; \r
QList<char>* patternOut = new QList<char>();\r
return patternOut;\r
}\r
\r
+QString FunctionalBlock::replaceExpressions(const QString& patternIn) throw(Exception) {\r
+\r
+ QString res = patternIn;\r
+ bool stop = false;\r
+ QRegularExpression re("[$][a-zA-Z0-9_]+");\r
+\r
+ while (!stop) {\r
+ stop = true;\r
+ QRegularExpressionMatchIterator matcher = re.globalMatch(res);\r
+ while(matcher.hasNext()) {\r
+ QRegularExpressionMatch m = matcher.next();\r
+ QString param = m.captured(0);\r
+ QString paramName = param;\r
+ paramName.remove(0,1);\r
+ BlockParameter* p = getParameterFromName(paramName);\r
+ if ((p != NULL) && (p->getType() == BlockParameter::Expression)) {\r
+ res.replace(param,p->getStringValue());\r
+ stop = false;\r
+ cout << "found an expr: " << qPrintable(paramName) << ", patern => " << qPrintable(res) << endl;\r
+ }\r
+ }\r
+ }\r
+ return res;\r
+}\r
+\r
QList<char> FunctionalBlock::expandPatternRecur(const QString& patternIn, int *offset) throw(Exception) {\r
\r
QList<char> patternOut;\r
*offset += 1;\r
}\r
if (*offset == patternIn.size()) {\r
- throw(Exception(INVALID_IFACE_PATTERN));\r
+ throw(Exception(INVALID_IFACE_PATTERN,this));\r
}\r
double repeat = 0;\r
try {\r
*offset += 1;\r
}\r
if (*offset == patternIn.size()) {\r
- throw(Exception(INVALID_IFACE_PATTERN));\r
+ throw(Exception(INVALID_IFACE_PATTERN,this));\r
}\r
double repeat = 0;\r
try {\r
foreach (QString name, varNames) {\r
QString paramName = name;\r
paramName.remove(0,1);\r
- BlockParameter* param = reference->getParameterFromName(paramName); \r
+ BlockParameter* param = getParameterFromName(paramName);\r
if (param == NULL) {\r
- throw(Exception(EVAL_PARAM_UNKNOWN));\r
+ throw(Exception(EVAL_PARAM_UNKNOWN,this));\r
}\r
bool okVal;\r
- int val = param->getDoubleValue(&okVal);\r
+ int val = param->getDoubleValue(&okVal); \r
if (!okVal) {\r
- throw(Exception(EVAL_PARAM_NOVALUE)); \r
+ throw(Exception(EVAL_PARAM_NOVALUE,this));\r
}\r
vars.insert(name,(double)val); \r
}\r
}\r
catch(int index) {\r
cerr << "Error at index " << index << ": " << qPrintable(evaluator->getError()) << endl;\r
- throw(Exception(EVAL_INVALID_EXPR));\r
+ throw(Exception(EVAL_INVALID_EXPR,this));\r
}\r
return result;\r
}\r
\r
+void FunctionalBlock::computeAdmittanceDelays() throw(Exception) {\r
+ static QString fctName = "FunctionalBlock::computeAdmittanceDelays()";\r
+#ifdef DEBUG_FCTNAME\r
+ cout << "call to " << qPrintable(fctName) << endl;\r
+#endif\r
+ QList<int> inClock;\r
+ QList<int> delays;\r
+\r
+ clearAdmittanceDelays();\r
+\r
+ // trying to synchronize the first one in AP\r
+ QMapIterator<AbstractInterface*,QList<char>* > iterAP(admittance);\r
+ QMapIterator<AbstractInterface*,QList<char>* > iterIP(inputPattern);\r
+\r
+ while (iterAP.hasNext()) {\r
+ iterAP.next();\r
+ iterIP.next();\r
+ QList<char>* ap = iterAP.value();\r
+ QList<char>* ip = iterIP.value();\r
+ int first = 0;\r
+ while ((first < lengthIP) && (ip->at(first) == 0)) first++;\r
+ while ((first < lengthAP) && (ap->at(first) == 0)) first--;\r
+ delays.append(first);\r
+ inClock.append(0);\r
+ QList<int>* delays = new QList<int>();\r
+ admittanceDelays.insert(iterAP.key(), delays);\r
+ }\r
+\r
+ QMapIterator<AbstractInterface*,QList<int>* > iterDelays(admittanceDelays);\r
+\r
+ // get the delay to apply\r
+ int maxDelay = 0;\r
+ for(int i=0;i<delays.size();i++) {\r
+ if (delays[i] > maxDelay) maxDelay = delays[i];\r
+ }\r
+ // adding the delays to IP\r
+ iterIP.toFront();\r
+ int i = 0;\r
+ while (iterIP.hasNext()) {\r
+ iterIP.next();\r
+ iterDelays.next();\r
+ QList<char>* ip = iterIP.value();\r
+ QList<int>* d = iterDelays.value();\r
+ d->append(maxDelay-delays[i]);\r
+ cout << "prependind " << qPrintable(iterIP.key()->getName()) << " with " << (maxDelay-delays[i]) << " 0" << endl;\r
+ for(int j=0;j<maxDelay-delays[i];j++) {\r
+ ip->prepend(0);\r
+ }\r
+ for(int j=0;j<delays[i];j++) {\r
+ ip->append(0);\r
+ }\r
+ i++;\r
+ }\r
+ lengthIP += maxDelay;\r
+\r
+ cout << "IP length = " << lengthIP << ", AP length = " << lengthAP << endl;\r
+ bool stop = false;\r
+ int apIndex = 0;\r
+ int ipIndex = 0;\r
+ while (!stop) {\r
+\r
+ // if AP is a valid group, search for the next valid group in IP\r
+ if (isValidDataGroup(admittance,apIndex)) {\r
+\r
+ while ((ipIndex < lengthIP) && (! isValidDataGroup(inputPattern,ipIndex))) ipIndex++;\r
+ if (ipIndex == lengthIP) {\r
+ stop = true;\r
+ continue;\r
+ }\r
+ }\r
+\r
+ iterAP.toFront();\r
+ iterIP.toFront();\r
+ iterDelays.toFront();\r
+\r
+ if (samePatterns(inputPattern,ipIndex,admittance,apIndex)) {\r
+ while (iterAP.hasNext()) {\r
+ iterAP.next();\r
+ iterDelays.next();\r
+ QList<char>* ap = iterAP.value();\r
+ if (ap->at(apIndex) == 1) {\r
+ QList<int>* d = iterDelays.value();\r
+ d->append(0); // the 1 is at its good place, so no delay\r
+ }\r
+ }\r
+ }\r
+ else {\r
+ cout << "diff between IP and AP at " << apIndex << endl;\r
+ // search for the next 1 in IP for every input that has a 1 in AP\r
+\r
+ while (iterAP.hasNext()) {\r
+ iterAP.next();\r
+ iterIP.next();\r
+ iterDelays.next();\r
+ QList<char>* ap = iterAP.value();\r
+ QList<char>* ip = iterIP.value();\r
+ QList<int>* d = iterDelays.value();\r
+ // case 1: 1 in IP is too late\r
+ if ((ap->at(apIndex) == 1) && (ip->at(ipIndex) == 0)) {\r
+ int delay = 1;\r
+ while ( ((ipIndex+delay) < lengthIP) && (ip->at(ipIndex+delay) == 0) ) delay++;\r
+ cout << "found a delay of " << (-delay) << " for iface " << qPrintable(iterAP.key()->getName()) << endl;\r
+ // moving the 1 to its normal pos.\r
+ ip->replace(ipIndex,1);\r
+ ip->replace(ipIndex+delay,0);\r
+ d->append(-delay);\r
+ }\r
+ // case 2: 1 in IP is too soon\r
+ else if ((ap->at(apIndex) == 0) && (ip->at(ipIndex) == 1)) {\r
+ int delay = 1;\r
+ while ( ((apIndex+delay) < lengthAP) && (ap->at(apIndex+delay) == 0) ) delay++;\r
+ cout << "found a delay of " << delay << " for iface " << qPrintable(iterAP.key()->getName()) << endl;\r
+ // search for next 0 in IP to put the 1\r
+ int k = ipIndex+delay;\r
+ while ((k < lengthIP) && (ip->at(k) == 1)) k++;\r
+ ip->replace(ipIndex,0);\r
+ ip->replace(k,1);\r
+ d->append(delay);\r
+ }\r
+ }\r
+ if (! samePatterns(inputPattern,inClock,admittance,apIndex)) {\r
+ cout << "Abnormal case while searching for delays" << endl;\r
+ }\r
+ }\r
+\r
+ apIndex++;\r
+ ipIndex++;\r
+ if ((apIndex >= lengthAP) || (ipIndex >= lengthIP)) stop = true;\r
+ }\r
+ iterDelays.toFront();\r
+ while (iterDelays.hasNext()) {\r
+ iterDelays.next();\r
+ QList<int>* d = iterDelays.value();\r
+ foreach(int v, *d) {\r
+ cout << v << " ";\r
+ }\r
+ cout << endl;\r
+ }\r
+\r
+}\r
+\r
void FunctionalBlock::createInputPattern() throw(Exception) {\r
static QString fctName = "FunctionalBlock::createInputPattern())";\r
#ifdef DEBUG_FCTNAME\r
#endif\r
\r
lengthIP = -1;\r
- foreach(AbstractInterface* iface, getControlInputs()) { \r
+ foreach(AbstractInterface* iface, getControlInputs()) {\r
+\r
ConnectedInterface* connIface = AI_TO_CON(iface);\r
+ // check if it is connected\r
+ if (connIface->getConnectedFrom() == NULL) {\r
+ throw(Exception(IFACE_NOT_CONNECTED,this));\r
+ }\r
+ // get the precursor output pattern\r
QList<char>* out = connIface->getConnectedFrom()->getOutputPattern();\r
+\r
+ ConnectedInterface* assoIface = AI_TO_CON(connIface->getAssociatedIface());\r
+ AbstractInputModifier* modifier = assoIface->getInputModifier();\r
+ // check if the input is modified\r
+ if (modifier != NULL) {\r
+\r
+ out = modifier->getModifiedInput(out);\r
+ }\r
+\r
if (out->size() == 0) {\r
clearInputPattern();\r
- throw(Exception(NO_IFACE_IP));\r
+ throw(Exception(NO_IFACE_IP,this));\r
}\r
if (lengthIP == -1) {\r
lengthIP = out->size();\r
while ((clock < lengthIP) && (! isValidDataGroup(inputPattern,clock))) clock++;\r
if (clock == lengthIP) {\r
cerr << "Abnormal case: end of IP has been reached without finding a valid group" << endl;\r
- throw(Exception(IP_END_NULLCOL)); \r
+ throw(Exception(IP_END_NULLCOL,this));\r
}\r
} \r
/* at that point 2 cases of compat : IP(clock) and AP(i) are equal valid group, or\r
*/\r
if (! samePatterns(inputPattern,clock,admittance,i)) {\r
cout << "AP(" << i << ") and IP(" << clock << ") are not equal" << endl;\r
- throw(Exception(IP_AP_NOTCOMPAT)); // IP and AP not compatible\r
+ throw(Exception(IP_AP_NOTCOMPAT,this)); // IP and AP not compatible\r
}\r
clock++;\r
i++;\r
}\r
if (clock < lengthIP) {\r
- throw(Exception(AP_TOO_SHORT));\r
+ throw(Exception(AP_TOO_SHORT,this));\r
cerr << "Abnormal case: AP is to short" << endl; \r
} \r
}\r
\r
// in case of inputPattern not created, do it\r
if (lengthIP <= 0) {\r
+\r
+ cout << "Strange case: input pattern is not created while it is time to compute output pattern !" << endl;\r
// collect the input patterns for each input \r
try {\r
createInputPattern();\r
return true;\r
}\r
\r
+bool FunctionalBlock::samePatterns(const QMap<AbstractInterface*, QList<char>* >& patternSrc, const QList<int> &srcCols, const QMap<AbstractInterface*, QList<char>* >& patternDest, int destCol) {\r
+ if (patternSrc.size() != srcCols.size()) return false;\r
+ if (patternSrc.size() != patternDest.size()) return false;\r
+\r
+ QMapIterator<AbstractInterface*, QList<char>* > iterSrc(patternSrc);\r
+ QListIterator<int> iterSrcCol(srcCols);\r
+ QMapIterator<AbstractInterface*, QList<char>* > iterDest(patternDest);\r
+ while (iterSrc.hasNext()) {\r
+ iterSrc.next();\r
+ int srcCol = iterSrcCol.next();\r
+ iterDest.next();\r
+ QList<char>* srcPat = iterSrc.value();\r
+ QList<char>* destPat = iterDest.value();\r
+ if (srcCol >= srcPat->size()) return false;\r
+ if (destCol >= destPat->size()) return false;\r
+ if (srcPat->at(srcCol) != destPat->at(destCol)) return false;\r
+ }\r
+ return true;\r
+}\r
+\r
bool FunctionalBlock::canCombinePatterns(const QMap<AbstractInterface*, QList<char>* >& patternSrc, int srcCol, QMap<AbstractInterface*, QList<char>* > patternDest, int destCol) {\r
if (patternSrc.size() != patternDest.size()) return false;\r
QMapIterator<AbstractInterface*, QList<char>* > iterSrc(patternSrc);\r
return false;\r
}\r
\r
+bool FunctionalBlock::isValidDataGroup(const QMap<AbstractInterface*, QList<char>* >& pattern, const QList<int> offsets) {\r
+ QMapIterator<AbstractInterface*, QList<char>* > iterSrc(pattern);\r
+ QListIterator<int> iterOffsets(offsets);\r
+ while (iterSrc.hasNext()) {\r
+ iterSrc.next();\r
+ int offset = iterOffsets.next();\r
+ QList<char>* srcPat = iterSrc.value();\r
+ if (offset >= srcPat->size()) return false;\r
+ if (srcPat->at(offset) == 1) return true;\r
+ }\r
+ return false;\r
+}\r
+\r
bool FunctionalBlock::isOnlyXDataGroup(const QMap<AbstractInterface *, QList<char> *> &pattern, int offset) {\r
QMapIterator<AbstractInterface*, QList<char>* > iterSrc(pattern); \r
while (iterSrc.hasNext()) {\r
lengthIP = -1;\r
}\r
\r
+void FunctionalBlock::clearAdmittanceDelays() {\r
+ QMapIterator<AbstractInterface*, QList<int>* > iterA(admittanceDelays);\r
+ while (iterA.hasNext()) {\r
+ iterA.next();\r
+ QList<int>* d = iterA.value();\r
+ if (d != NULL) delete d;\r
+ }\r
+ admittanceDelays.clear();\r
+}\r
+\r
int FunctionalBlock::createTriggers() {\r
triggers.clear();\r
/* NB: this method returns the number of executions that have been started\r
inline QList<int> getProductionCounter() { return productionCounter; }\r
inline QMap<AbstractInterface*, QList<char>* > getConsumptionPattern() { return consumptionPattern; }\r
inline QMap<AbstractInterface*, QList<char>* > getProductionPattern() { return productionPattern; }\r
+ inline QMap<AbstractInterface*, QList<int>* > getAdmittanceDelays() { return admittanceDelays; }\r
inline int getConsumptionPatternLength() { return lengthCP; }\r
inline int getProductionPatternLength() { return lengthPP; }\r
inline int getDelta() { return delta; }\r
void createPatterns() throw(Exception); // called in Graph, before checking compatibility and computing output pattern\r
void checkInputPatternCompatibility() throw(Exception);\r
void computeOutputPattern(int nbExec = -1) throw(Exception);\r
- \r
+ void computeAdmittanceDelays() throw(Exception); // compute differences between IP and admittance\r
+\r
private: \r
// patterns\r
void createDelta() throw(Exception);\r
void createProductionPattern() throw(Exception); // initialize a QList<char> for each interface from patterns defined in implementation\r
void createProductionCounter() throw(Exception); // initialize a QList<int> from counter defined in implementation\r
void createAdmittance(int nbExec) throw(Exception); // initialize a QList<char> from consumption pattern and delta\r
+\r
void clearConsumptionPattern();\r
void clearProductionPattern();\r
void createInputPattern() throw(Exception);\r
void clearInputPattern();\r
+ void clearAdmittanceDelays();\r
int createTriggers(); // compute the clock cycle at which the block is triggered\r
\r
double evaluateExpression(const QString& expression) throw(Exception);\r
QList<char>* expandPattern(const QString& patternIn) throw(Exception);\r
QList<char> expandPatternRecur(const QString& patternIn, int* offset) throw(Exception);\r
+ QString replaceExpressions(const QString& patternIn) throw(Exception);\r
/*!\r
* \brief samePatterns\r
* \param patternSrc the pattern that must be tested with patternDest (is patternDest == patternDest) \r
leaving the dest pattern in an inconsistent state. Thus, it is a good idea to call canCombine before.\r
*/\r
bool samePatterns(const QMap<AbstractInterface*, QList<char>* >& patternSrc, int srcCol, const QMap<AbstractInterface*, QList<char>* >& patternDest, int destCol);\r
+ bool samePatterns(const QMap<AbstractInterface*, QList<char>* >& patternSrc, const QList<int>& srcCols, const QMap<AbstractInterface*, QList<char>* >& patternDest, int destCol);\r
/*!\r
* \brief canCombinePatterns\r
* \param patternSrc the pattern that must be combined with patternDest (patternDest = patternDest OR patternSrc) \r
* isValidGroup checks if there is at least one 1 in the column offset of pattern.\r
*/\r
bool isValidDataGroup(const QMap<AbstractInterface*, QList<char>* >& pattern, int offset);\r
+ bool isValidDataGroup(const QMap<AbstractInterface*, QList<char>* >& pattern, const QList<int> offsets);\r
/*!\r
* \brief isOnlyXGroup\r
* \param pattern the pattern to test\r
void shiftRightPattern(const QMap<AbstractInterface*, QList<char>* >& pattern, int offset);\r
\r
QMap<AbstractInterface*, QList<char>* > consumptionPattern;\r
- QMap<AbstractInterface*, QString > admittanceCyclic; // the admittance expressed as prologue-cyclic part-eppilogue, deduced from admittance\r
+ QMap<AbstractInterface*, QString > admittanceCyclic; // the admittance expressed as prologue-cyclic part-epilogue, deduced from admittance\r
QMap<AbstractInterface*, QList<char>* > admittance; // the admittance taking into account nb exec.\r
+ QMap<AbstractInterface*, QList<int>* > admittanceDelays; // the delay between what should be consumed and IP\r
QMap<AbstractInterface*, QList<char>* > productionPattern;\r
QMap<AbstractInterface*,QList<char>* > inputPattern;\r
QMap<AbstractInterface*, QList<char>* > outputPattern; // CAUTION: the QList<char>* must also be stored in the outputPattern attributes of AbstractInterface\r
reference = _reference;\r
\r
name = reference->getName();\r
+ type = reference->getType();\r
endianess = reference->getEndianess();\r
width = reference->getWidth();\r
direction = reference->getDirection();\r
void Graph::resetPatternComputed() {
foreach(AbstractBlock* block, sources) {
block->setPatternComputed(false);
+ block->resetTraversalLevel();
}
foreach(AbstractBlock* block, groups) {
GroupBlock* group = AB_TO_GRP(block);
group->setPatternComputed(false);
+ block->resetTraversalLevel();
foreach(AbstractBlock* inBlock, group->getBlocks()) {
inBlock->setPatternComputed(false);
+ block->resetTraversalLevel();
}
}
}
throw(e);
}
- resetPatternComputed();
+ resetPatternComputed();
// search for all block that are generators.
QList<FunctionalBlock*> generators;
generators.append(sources);
GroupBlock::GroupBlock(GroupBlock *_parent) throw(Exception) : AbstractBlock() {
// force topGroup to false if this group has a parent
- if (_parent != NULL) {
+ if (_parent != NULL) {
topGroup = false;
name = QString("sub_group")+"_"+QString::number(counter++);
}
void GroupBlock::createInputPattern() {
foreach(AbstractInterface* iface, getControlInputs()) {
ConnectedInterface* connIface = AI_TO_CON(iface);
- QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
- connIface->setOutputPattern(pattern);
- }
+ QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
+ connIface->setOutputPattern(pattern);
+ }
+}
+
+void GroupBlock::computeAdmittanceDelays() throw(Exception) {
+ throw(Exception(INVALID_GROUPBLOCK_USE));
}
-void GroupBlock::checkInputPatternCompatibility() throw(Exception){
+void GroupBlock::checkInputPatternCompatibility() throw(Exception){
+ throw(Exception(INVALID_GROUPBLOCK_USE));
}
+
void GroupBlock::computeOutputPattern(int nbExec) throw(Exception) {
static QString fctName = "GroupBlock::computeOutputPattern()";
cout << "computing output pattern of group " << qPrintable(name) << endl;
- bool canCompute = false;
+ bool canCompute = false;
// get the input pattern on each inputs
createInputPattern();
// find blocks that are connected to that inputs and generators
QList<AbstractBlock*> fifo;
foreach(AbstractBlock* block, blocks) {
-
+
bool addIt = false;
// if a block is a generator and has control outputs, add it
if (block->isGeneratorBlock()) {
if (block->getControlOutputs().size() > 0) addIt = true;
}
else {
- // if the block has a control input connected from an intput of the group, add it too
+ // if the block has all its connected inputs that are connected to an intput of the group, add it too
+ addIt = true;
foreach(AbstractInterface* iface, block->getControlInputs()) {
- //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+ //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
//cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
- if (connFrom->getOwner() == this) {
- addIt = true;
+ if (connFrom == NULL) {
+ addIt = false;
+ break;
+ }
+ else if (connFrom->getOwner() != this) {
+ addIt = false;
break;
}
}
}
if (addIt) {
cout << "adding " << qPrintable(block->getName()) << " to initialize the FIFO" << endl;
- fifo.append(block);
+ block->setTraversalLevel(0); // level 0 = first blocks to be evaluated
+ fifo.append(block);
}
}
AbstractBlock* block = fifo.takeFirst();
if (block->getPatternComputed()) continue; // block has already been processed
+
+ cout << "computing compat and output for " << qPrintable(block->getName()) << endl;
+
try {
block->checkInputPatternCompatibility();
}
- catch(Exception e) {
- cout << qPrintable(block->getName()) << " is not compatible with his input pattern" << endl;
+ catch(Exception e) {
+ cout << qPrintable(block->getName()) << " is not compatible with its input pattern" << endl;
throw(e);
- }
+ }
try {
block->computeOutputPattern();
}
- catch(Exception e) {
+ catch(Exception e) {
cout << "cannot finalize output pattern computation of " << qPrintable(block->getName()) << endl;
- throw(e);
+ throw(e);
}
canCompute = true;
block->setPatternComputed(true);
- // add other blocks connected from block to the fifo
+ /* add other blocks connected from block to the fifo but only if
+ all their connected inputs are connected to blocks that have
+ a traversalLevel >=0
+ */
foreach(AbstractInterface* iface, block->getControlOutputs()) {
ConnectedInterface* conn = (ConnectedInterface*)iface;
foreach(ConnectedInterface* connTo, conn->getConnectedTo()) {
- /* if connTo is owned by a functional block
- or by a group block that is within this, add the block to the fifo.
- */
- if (connTo->getOwner()->isFunctionalBlock()) {
- fifo.append(connTo->getOwner());
+
+ AbstractBlock* block1 = connTo->getOwner();
+ cout << "testing if " << qPrintable(block1->getName()) << " has all connected inputs connected to already processed blocks" << endl;
+ bool addIt = true;
+ int maxLevel = 0;
+
+ foreach(AbstractInterface* iface, block1->getControlInputs()) {
+ //cout << qPrintable(iface->getName()) << " of " << qPrintable(iface->getOwner()->getName()) << " connected to " << endl;
+ ConnectedInterface* connFrom = ((ConnectedInterface*)iface)->getConnectedFrom();
+ //cout << qPrintable(connFrom->getName()) << " of " << qPrintable(connFrom->getOwner()->getName()) << endl;
+
+ if ((connFrom != NULL) && (connFrom->getOwner()->getPatternComputed() == false)) {
+ addIt = false;
+ break;
+ }
+ else {
+ if (connFrom->getOwner()->getTraversalLevel() > maxLevel) maxLevel = connFrom->getOwner()->getTraversalLevel();
+ }
+ }
+
+ if (addIt) {
+ cout << "adding " << qPrintable(block1->getName()) << " to the FIFO" << endl;
+ block1->setTraversalLevel(maxLevel+1); // level 0 = first blocks to be evaluated
+ fifo.append(block1);
}
- else if (connTo->getOwner() != this) {
- fifo.append(connTo->getOwner());
- }
}
}
}
-
+
if (canCompute) {
foreach(AbstractInterface* iface, getControlOutputs()) {
ConnectedInterface* connIface = AI_TO_CON(iface);
QList<char>* pattern = new QList<char>(*(connIface->getConnectedFrom()->getOutputPattern()));
- connIface->setOutputPattern(pattern);
+ connIface->setOutputPattern(pattern);
}
setPatternComputed(true);
- }
+ }
+
}
void checkInputPatternCompatibility() throw(Exception);
void computeOutputPattern(int nbExec = -1) throw(Exception);
+ void computeAdmittanceDelays() throw(Exception);
private:
// patterns
void GroupWidget::createToolbar() {
toolbarEditMode = new QToolBar(tr("Mode"));
toolbarAdd = new QToolBar(tr("Group"));
- toolbarTools = new QToolBar(tr("Tools"));
+ //toolbarTools = new QToolBar(tr("Tools"));
toolbarEditMode->addWidget(new QLabel("Mode"));
- toolbarTools->addWidget(new QLabel("Tools"));
+ //toolbarTools->addWidget(new QLabel("Tools"));
toolbarEditMode->addSeparator();
- toolbarTools->addSeparator();
+ //toolbarTools->addSeparator();
toolbarEditMode->addWidget(butAddConnection);
toolbarEditMode->addWidget(butEdit);
toolbarAdd->addAction(newEmptyGroupAct);
toolbarAdd->addAction(newGroupAct);
- toolbarTools->addAction(deleteAct);
- toolbarTools->addAction(selectAllAct);
- toolbarTools->addAction(unselectAllAct);
+ //toolbarTools->addAction(deleteAct);
+ //toolbarTools->addAction(selectAllAct);
+ //toolbarTools->addAction(unselectAllAct);
layout->addWidget(toolbarEditMode,0,0);
layout->addWidget(toolbarAdd,0,1);
- layout->addWidget(toolbarTools,0,2);
+ //layout->addWidget(toolbarTools,0,2);
}
void GroupWidget::slotEdit() {
painter->drawPath(params->outArrow);
}
+ // paint modifier box if needed
+
+ if (refInter->getInputModifier() != NULL) {
+ painter->save();
+ painter->translate(params->arrowWidth+params->arrowLineLength,0);
+ painter->drawRect(0,-5,10,10);
+ painter->restore();
+ }
+
+
// draw names
if(selected) {
painter->setPen(QPen(Qt::red,2));
else if((owner->isBoxItem()) || (owner->isSourceItem())){
painter->drawText(-w,-h/2,w,h,Qt::AlignLeft | Qt::TextWordWrap, refInter->getName());
}
- }
+ }
+
+
painter->restore();
}
layout->addWidget(new QLabel(inter->refInter->getDirectionString()), 4, 1);
layout->addWidget(new QLabel("Purpose :"), 5, 0);
layout->addWidget(new QLabel(inter->refInter->getPurposeString()), 5, 1);
+ layout->addWidget(new QLabel("Type :"), 6, 0);
+ layout->addWidget(new QLabel(inter->refInter->getTypeString()), 6, 1);
+
this->setLayout(layout);
show();
#include "GroupWidget.h"
#include "GroupScene.h"
#include "VHDLConverter.h"
-#include "AbstractBoxItem.h"
#include "Graph.h"
-#include "GroupItem.h"
+#include "FunctionalBlock.h"
#include <QDomDocument>
#include <QDomElement>
#include <QDomText>
cout << "all references and implementations are loaded" << endl;
+ params->createDelayBlock();
+
// create the menu, action, ...
dispatcher = new Dispatcher(params,this);
params->setDispatcher(dispatcher);
void MainWindow::initialize() {
projectMenuEnb = 0;
+ analysisMenuEnb = 0;
stackedWidget->setCurrentIndex(0);
enableProjectActions(true,PROJECT_NEW | PROJECT_OPEN, OP_RAZ);
+ enableAnalysisActions(false);
stackedWidget->setCurrentIndex(0);
}
}
+void MainWindow::enableAnalysisActions(bool enbMenu, quint16 mask, quint8 op) {
+ if (enbMenu) {
+ analysisMenu->setEnabled(true);
+ }
+ else {
+ analysisMenu->setEnabled(false);
+ }
+
+ if (op == OP_ADD) {
+ analysisMenuEnb = analysisMenuEnb | mask;
+ }
+ else if (op == OP_REM) {
+ analysisMenuEnb = (analysisMenuEnb | mask) ^ mask;
+ }
+ else if (op == OP_RAZ) {
+ analysisMenuEnb = mask;
+ }
+
+
+ if (analysisMenuEnb & ANALYSIS_ANALYZE) {
+ graphAnalysis->setEnabled(true);
+ }
+ else {
+ graphAnalysis->setEnabled(false);
+ }
+}
+
void MainWindow::createMenus(){
allMenuBar = menuBar();
projectMenu = allMenuBar->addMenu(tr("&Project"));
+ analysisMenu = allMenuBar->addMenu(tr("&Analysis"));
toolsMenu = allMenuBar->addMenu(tr("&Tools"));
projectMenu->addAction(newProject);
projectMenu->addAction(closeProject);
projectMenu->addAction(openLibrary);
- toolsMenu->addAction(newBlockWidgetAct);
- toolsMenu->addAction(graphValidation);
+ analysisMenu->addAction(graphAnalysis);
+
+ toolsMenu->addAction(vhdlToXmlAct);
+
}
openLibrary->setStatusTip(tr("Open block library window"));
connect(openLibrary, SIGNAL(triggered()), this, SLOT(slotOpenBlockLibrary()));
- newBlockWidgetAct = new QAction(tr("&XML generator"), this);
- newBlockWidgetAct->setIcon(QPixmap::fromImage(QImage("icons/new.ico")));
- newBlockWidgetAct->setStatusTip(tr("Create a new XML generator"));
- connect(newBlockWidgetAct, SIGNAL(triggered()), this, SLOT(slotNewBlockWidget()));
+ vhdlToXmlAct = new QAction(tr("&XML generator"), this);
+ vhdlToXmlAct->setIcon(QPixmap::fromImage(QImage("icons/new.ico")));
+ vhdlToXmlAct->setStatusTip(tr("Create a new XML generator"));
+ connect(vhdlToXmlAct, SIGNAL(triggered()), this, SLOT(slotVHDLToXml()));
- graphValidation = new QAction(tr("&graph validation"), this);
- graphValidation->setIcon(QPixmap::fromImage(QImage("icons/new.ico")));
- graphValidation->setStatusTip(tr("validate the graph"));
- connect(graphValidation, SIGNAL(triggered()), this, SLOT(slotGraphValidation()));
+ graphAnalysis = new QAction(tr("&graph validation"), this);
+ graphAnalysis->setIcon(QPixmap::fromImage(QImage("icons/new.ico")));
+ graphAnalysis->setStatusTip(tr("validate the graph"));
+ connect(graphAnalysis, SIGNAL(triggered()), this, SLOT(slotGraphAnalysis()));
}
library->updateComboScene();
params->isCurrentProject = true;
enableProjectActions(true, PROJECT_CLOSE | PROJECT_SAVE | PROJECT_SAVEAS | PROJECT_LIB, OP_RAZ);
+ enableAnalysisActions(true, ANALYSIS_ANALYZE, OP_RAZ);
}
else {
QMessageBox msgBox;
void MainWindow::slotNewProject(){
enableProjectActions(true, PROJECT_CLOSE | PROJECT_SAVE | PROJECT_SAVEAS | PROJECT_LIB, OP_RAZ);
+ enableAnalysisActions(true, ANALYSIS_ANALYZE, OP_RAZ);
GroupWidget* topGroup = dispatcher->createTopScene();
addTopGroup(topGroup);
library->updateComboScene();
}
-void MainWindow::slotNewBlockWidget() {
+void MainWindow::slotVHDLToXml() {
new VHDLConverter();
}
}
-void MainWindow::slotGraphValidation() {
- try {
- params->getGraph()->computeOutputPatterns(5);
+void MainWindow::slotGraphAnalysis() {
+ bool compat = true;
+ try {
+ params->getGraph()->computeOutputPatterns(1);
}
catch(Exception e) {
- cerr << qPrintable(e.getMessage()) << endl;
+ cerr << qPrintable(e.getMessage()) << endl;
+ compat = false;
+ if (e.getType() == IP_AP_NOTCOMPAT) {
+ FunctionalBlock* toBlock = (FunctionalBlock*)(e.getSource());
+ QString msg = tr("");
+ msg.append(toBlock->getName());
+ msg += " is not compatible with its input pattern.\nDo you want to launch automatic modification process to ensure the compatibility ?";
+ int ret = QMessageBox::question(this,tr("Building references library"),msg, QMessageBox::Ok | QMessageBox::Cancel, QMessageBox::Ok);
+ if (ret == QMessageBox::Ok) {
+ dispatcher->findGraphModifications(toBlock);
+ }
+ }
}
}
// defines for menus
-#define TRACE_MENU (quint8)1
+#define PROJECT_MENU (quint8)1
+#define ANALYSIS_MENU (quint8)2
+#define TOOLS_MENU (quint8)3
// defines for actions
#define NONE_ACT (quint16)0
#define PROJECT_CLOSE (quint16)16
#define PROJECT_LIB (quint16)32
+#define ANALYSIS_ANALYZE (quint16)1
+
#define OP_ADD (quint8)0
#define OP_REM (quint8)1
#define OP_RAZ (quint8)2
QMenu* projectMenu;
quint16 projectMenuEnb;
+ QMenu* analysisMenu;
+ quint16 analysisMenuEnb;
QMenu* toolsMenu;
+ // actions for project
QAction* newProject;
QAction* openProject;
QAction* saveProject;
QAction* closeProject;
QAction* openLibrary;
- QAction *newBlockWidgetAct;
- QAction *graphValidation;
+ // actions for graph analysis
+ QAction *graphAnalysis;
+ // actions for tools
+ QAction *vhdlToXmlAct;
// versioning related
quint8 versionMaj;
public slots:
void enableProjectActions(bool enbMenu, quint16 mask = 0, quint8 op = 0); // default : add nothing
+ void enableAnalysisActions(bool enbMenu, quint16 mask = 0, quint8 op = 0); // default : add nothing
private slots:
void slotNewProject();
bool slotCloseProject();
void slotOpenBlockLibrary();
- void slotNewBlockWidget();
- void slotGraphValidation();
+ void slotGraphAnalysis();
+
+ void slotVHDLToXml();
void slotCheckNewVersion(QNetworkReply *reply);
};
#include "Exception.h"\r
#include "BlocksToConfigureWidget.h"\r
\r
+#include "BlockParameterGeneric.h"\r
+\r
+#include "DelayInputModifier.h"\r
+\r
Parameters::Parameters() {\r
categoryTree = NULL;\r
arrowWidth = 5;\r
return ref;\r
}\r
\r
+void Parameters::createDelayBlock() {\r
+ delayRef = new ReferenceBlock("no.xml");\r
+ delayRef->addCategory(100);\r
+ delayRef->setName("delay");\r
+\r
+ BlockCategory* cat = categoryTree->searchCategory(100);\r
+ cat->blocks.append(delayRef);\r
+\r
+ AbstractInterface* interIn = new ReferenceInterface(delayRef,"data_in",AbstractInterface::Input, AbstractInterface::Data, "expression","$in_width");\r
+ delayRef->addInterface(interIn);\r
+ AbstractInterface* interInCtl = new ReferenceInterface(delayRef,"data_in_enb",AbstractInterface::Input, AbstractInterface::Control, "boolean","1");\r
+ delayRef->addInterface(interInCtl);\r
+ interInCtl->setAssociatedIface(interIn);\r
+ AbstractInterface* interOut = new ReferenceInterface(delayRef,"data_out",AbstractInterface::Output, AbstractInterface::Data, "expression","$in_width");\r
+ delayRef->addInterface(interOut);\r
+ AbstractInterface* interOutCtl = new ReferenceInterface(delayRef,"data_out_enb",AbstractInterface::Output, AbstractInterface::Control, "boolean","1");\r
+ delayRef->addInterface(interOutCtl);\r
+ interOutCtl->setAssociatedIface(interOut);\r
+ BlockParameter* param1 = new BlockParameterGeneric(delayRef,"in_width","natural","8");\r
+ BlockParameter* param2 = new BlockParameterGeneric(delayRef,"dly_length","natural","1");\r
+ delayRef->addParameter(param1);\r
+ delayRef->addParameter(param2);\r
+ delayImpl = new BlockImplementation("no.xml");\r
+ delayImpl->setDelta("1");\r
+ QHash<QString,QString> consPattern;\r
+ consPattern.insert("data_in_enb","1");\r
+ delayImpl->setConsumptionPattern(consPattern);\r
+ QHash<QString,QString> prodPattern;\r
+ prodPattern.insert("data_out_enb","O{$dly_length}1");\r
+ delayImpl->setProductionPattern(prodPattern);\r
+ delayImpl->setProductionCounter("1");\r
+ delayRef->addImplementation(delayImpl);\r
+ delayImpl->setReference(delayRef);\r
+ if (! delayImpl->checkPatterns()) {\r
+ cout << "Delay block creation: failure" << endl;\r
+ }\r
+ else {\r
+ cout << "Delay block creation: success" << endl;\r
+ }\r
+\r
+}\r
+\r
\r
\r
void Parameters::validateXmlFile(const QString& xmlFileName, const QString& xsdFileName, XmlFileType fileType) throw(Exception) {\r
}\r
cout << "connections loaded and created succefully!" << endl;\r
\r
+ QDomNodeList modifierNodes = root.elementsByTagName("modifier");\r
+\r
+ for(int i=0; i<modifierNodes.length(); i++){\r
+ QDomElement currentModifierNode = modifierNodes.at(i).toElement();\r
+\r
+ int id = currentModifierNode.attribute("id","none").toInt(&ok);\r
+ if(!ok) throw(Exception(PROJECTFILE_CORRUPTED));\r
+\r
+ QString typeStr = currentModifierNode.attribute("type","none");\r
+ if(!ok) throw(Exception(PROJECTFILE_CORRUPTED));\r
+ QString paramsStr = currentModifierNode.attribute("params","none");\r
+ if(!ok) throw(Exception(PROJECTFILE_CORRUPTED));\r
+\r
+ AbstractInputModifier* mod = NULL;\r
+ if (typeStr == "delay") {\r
+ int delay = paramsStr.toInt(&ok);\r
+ if(!ok) throw(Exception(PROJECTFILE_CORRUPTED));\r
+ mod = new DelayInputModifier(delay);\r
+ }\r
+\r
+ /* NB: just adding delays for now. To be cont'd */\r
+ InterfaceItem *iface = searchInterfaceItemById(id,topScene);\r
+\r
+ if(iface != NULL ) {\r
+ iface->refInter->setInputModifier(mod);\r
+\r
+ } else {\r
+ cout << "interfaces not found, modifiers setup canceled!" << endl;\r
+ }\r
+ }\r
+ cout << "modifiers loaded and created succefully!" << endl;\r
+\r
return topGroup;\r
}\r
\r
QString line = in.readLine();\r
line = in.readLine();\r
\r
- if (!line.contains("<block>")) {\r
+ if (!line.contains("<block")) {\r
blockXML.close();\r
continue;\r
}\r
}\r
\r
writer.writeEndElement(); //</connections>\r
+\r
+ QList<InterfaceItem *> lstIfaceItem;\r
+ // search for modifiers\r
+ foreach(ConnectionItem* item, allConnections) {\r
+ InterfaceItem* fromIfaceItem = item->getFromInterfaceItem();\r
+ AbstractInputModifier* mod = fromIfaceItem->refInter->getInputModifier();\r
+ if (mod != NULL) {\r
+ if (!lstIfaceItem.contains(fromIfaceItem)) lstIfaceItem.append(fromIfaceItem);\r
+ }\r
+ InterfaceItem* toIfaceItem = item->getToInterfaceItem();\r
+ mod = toIfaceItem->refInter->getInputModifier();\r
+ if (mod != NULL) {\r
+ if (!lstIfaceItem.contains(toIfaceItem)) lstIfaceItem.append(toIfaceItem);\r
+ }\r
+ }\r
+ // write input modifiers\r
+ writer.writeStartElement("modifiers");\r
+ foreach(InterfaceItem* item, lstIfaceItem) {\r
+ AbstractInputModifier* mod = item->refInter->getInputModifier();\r
+ if (mod != NULL) {\r
+ writer.writeStartElement("modifier");\r
+ writer.writeAttribute("id", QString::number(item->getId()));\r
+ writer.writeAttribute("type",mod->getTypeStr());\r
+ writer.writeAttribute("params", mod->getParametersStr());\r
+ writer.writeEndElement();\r
+ }\r
+ }\r
+\r
+ writer.writeEndElement(); //</modifiers>\r
writer.writeEndElement(); //</blast_project\r
\r
writer.writeEndDocument();\r
return NULL;\r
}\r
\r
+BoxItem* Parameters::searchFunctionalBlock(AbstractBlock* block) {\r
+\r
+ return searchFunctionalBlockRecur(block,topScene);\r
+}\r
+\r
+BoxItem* Parameters::searchFunctionalBlockRecur(AbstractBlock* block, GroupScene* scene) {\r
+\r
+ foreach(BoxItem *item, scene->getBoxItems()){\r
+ if(item->getRefBlock() == block) {\r
+ return item;\r
+ }\r
+ }\r
+\r
+ BoxItem* item = NULL;\r
+ foreach(GroupScene *s, scene->getChildrenScene()) {\r
+ item = searchFunctionalBlockRecur(block,s);\r
+ if (item != NULL) return item;\r
+ }\r
+ return NULL;\r
+}\r
+\r
InterfaceItem* Parameters::searchInterfaceItemById(int id, GroupScene* scene) {\r
\r
foreach(InterfaceItem *item, scene->getGroupItem()->getInterfaces()){\r
class GroupBlock;\r
class FunctionalBlock;\r
class GroupScene;\r
+class AbstractBoxItem;\r
class GroupItem;\r
class BoxItem;\r
class InterfaceItem;\r
QList<QString> implPathes;\r
QList<ReferenceBlock*> availableBlocks;\r
QList<BlockImplementation*> availableImplementations;\r
-\r
+ ReferenceBlock* delayRef;\r
+ BlockImplementation* delayImpl; \r
\r
QString refLib;\r
QString implLib;\r
EditState editState; // takes values from EDIT_STATE_XXX\r
bool unsaveModif;\r
bool isRstClkShown;\r
+ QMap<FunctionalBlock*, BoxItem*> blockToItem; // allow to retrieve a box item from a functionnal block\r
\r
Graph* createGraph();\r
void destroyGraph();\r
void loadReferencesFromXml() throw(Exception);\r
void loadReferencesFromLib() throw(Exception);\r
void saveReferencesToLib() throw(Exception);\r
+ void createDelayBlock();\r
\r
void loadImplementationsFromXml() throw(Exception);\r
void loadImplementationsFromLib() throw(Exception);\r
ReferenceBlock* searchBlockByXml(QString xmlName);\r
ReferenceBlock* searchBlockByMd5(QString sumMd5);\r
\r
+ BoxItem* searchFunctionalBlock(AbstractBlock* block);\r
+\r
void save(QString confFile);\r
\r
\r
\r
GroupScene* searchSceneById(int id, GroupScene* scene);\r
BoxItem* searchBlockItemById(int id, GroupScene* scene);\r
+ BoxItem* searchFunctionalBlockRecur(AbstractBlock* block, GroupScene* scene);\r
GroupItem* searchGroupItemById(int id, GroupScene* scene);\r
InterfaceItem* searchInterfaceItemById(int id, GroupScene *scene);\r
\r
#include "AbstractBlock.h"
ParametersWindow::ParametersWindow(AbstractBlock *_block, Parameters *_params, BlocksToConfigureWidget *btcw, QWidget *parent) :
- QWidget(parent)
-{
+ QWidget(parent) {
block = _block;
confWidget = btcw;
params = _params;
show();
}
-void ParametersWindow::updateData()
-{
+void ParametersWindow::updateData() {
BlockParameter *param = block->getParameters().at(comboBox->currentIndex());
name->setText(param->getName());
value->setText(param->getValue().toString());
QString idsStr = eltCat.attribute("ids","none");
if (idsStr == "none") throw (Exception(BLOCKFILE_CORRUPTED));
- QStringList listCat = idsStr.split(",");
- foreach(QString str, listCat)
- {
- int idCat = str.toInt(&ok);
- categories.append(idCat);
+ if (idsStr.isEmpty()) {
+ categories.append(99);
+ }
+ else {
+ QStringList listCat = idsStr.split(",");
+ foreach(QString str, listCat)
+ {
+ int idCat = str.toInt(&ok);
+ categories.append(idCat);
+ }
}
// getting description
ReferenceInterface *iface = (ReferenceInterface *)(b.inputs.at(i));
if (iface->getPurpose() == AbstractInterface::Control) {
toWrite << iface->getName();
+ toWrite << iface->getType();
toWrite << iface->getWidth();
toWrite << iface->getPurpose();
toWrite << iface->getDirection();
ReferenceInterface *iface = (ReferenceInterface *)(b.inputs.at(i));
if (iface->getPurpose() != AbstractInterface::Control) {
toWrite << iface->getName();
+ toWrite << iface->getType();
toWrite << iface->getWidth();
toWrite << iface->getPurpose();
toWrite << iface->getDirection();
ReferenceInterface *iface = (ReferenceInterface *)(b.outputs.at(i));
if (iface->getPurpose() == AbstractInterface::Control) {
toWrite << iface->getName();
+ toWrite << iface->getType();
toWrite << iface->getWidth();
toWrite << iface->getPurpose();
toWrite << iface->getDirection();
ReferenceInterface *iface = (ReferenceInterface *)(b.outputs.at(i));
if (iface->getPurpose() != AbstractInterface::Control) {
toWrite << iface->getName();
+ toWrite << iface->getType();
toWrite << iface->getWidth();
toWrite << iface->getPurpose();
toWrite << iface->getDirection();
for(int i=0; i<b.bidirs.size(); i++){
ReferenceInterface *iface = (ReferenceInterface *)(b.bidirs.at(i));
toWrite << iface->getName();
+ toWrite << iface->getType();
toWrite << iface->getWidth();
toWrite << iface->getPurpose();
toWrite << iface->getDirection();
iface = new ReferenceInterface(&b);
in >> txt;
iface->setName(txt);
+ int type;
+ in >> type;
+ iface->setType(type);
in >> txt;
iface->setWidth(txt);
in >> val;
iface = new ReferenceInterface(&b);
in >> txt;
iface->setName(txt);
+ int type;
+ in >> type;
+ iface->setType(type);
in >> txt;
iface->setWidth(txt);
in >> val;
iface = new ReferenceInterface(&b);
in >> txt;
iface->setName(txt);
+ int type;
+ in >> type;
+ iface->setType(type);
in >> txt;
iface->setWidth(txt);
in >> val;
// does strictly nothing
throw(Exception(INVALID_REFBLOCK_USE));
}
+
+void ReferenceBlock::computeAdmittanceDelays() throw(Exception) {
+ // does strictly nothing
+ throw(Exception(INVALID_REFBLOCK_USE));
+}
// patterns
void checkInputPatternCompatibility() throw(Exception);
void computeOutputPattern(int nbExec = -1) throw(Exception);
+ void computeAdmittanceDelays() throw(Exception);
};
#endif // __REFERENCEBLOCK_H__
BlockParameter *blockParam = NULL;
blockParam = functionalBlock->getParameterFromName(name);
if (blockParam == NULL) throw(Exception(PROJECTFILE_CORRUPTED));
- blockParam->setValue(value);
+ blockParam->setValue(value);
}
// recreate all (non-control) interfaces because of some may have a multiplicity>1 with several examplars
void VHDLConverter::updateArchitecture() {\r
QRegularExpression rxLT("<=",QRegularExpression::CaseInsensitiveOption);\r
QRegularExpression rxGT("=>",QRegularExpression::CaseInsensitiveOption);\r
- foreach(QString line, archLines) {\r
+ for(int i=0;i<archLines.size();i++) {\r
+ QString line = archLines.at(i);\r
replaceSignalNames(line);\r
- line.replace(rxLT,"<=");\r
- line.replace(rxGT,"=>");\r
-\r
+ //line.replace(rxLT,"<=");\r
+ //line.replace(rxGT,"=>");\r
+ archLines.replace(i,line);\r
cout << qPrintable(line) << endl;\r
}\r
}\r
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject>
-<!-- Written by QtCreator 4.2.0, 2017-12-08T17:50:18. -->
+<!-- Written by QtCreator 4.2.0, 2018-01-15T00:01:27. -->
<qtcreator>
<data>
<variable>EnvironmentId</variable>
- <value type="QByteArray">{3701e197-5b6c-48ea-9e98-a6cf6de18672}</value>
+ <value type="QByteArray">{c8006d66-d34f-42be-ad10-d0207752286d}</value>
</data>
<data>
<variable>ProjectExplorer.Project.ActiveTarget</variable>
<valuemap type="QVariantMap">
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Desktop</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Desktop</value>
- <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{ed04208c-8774-456b-99b9-4a02094ca7a4}</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{2c9bf876-3476-44eb-8065-1f0844704dda}</value>
<value type="int" key="ProjectExplorer.Target.ActiveBuildConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveDeployConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveRunConfiguration">0</value>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE QtCreatorProject>
+<!-- Written by QtCreator 4.2.0, 2017-10-13T10:38:54. -->
+<qtcreator>
+ <data>
+ <variable>EnvironmentId</variable>
+ <value type="QByteArray">{3701e197-5b6c-48ea-9e98-a6cf6de18672}</value>
+ </data>
+ <data>
+ <variable>ProjectExplorer.Project.ActiveTarget</variable>
+ <value type="int">0</value>
+ </data>
+ <data>
+ <variable>ProjectExplorer.Project.EditorSettings</variable>
+ <valuemap type="QVariantMap">
+ <value type="bool" key="EditorConfiguration.AutoIndent">true</value>
+ <value type="bool" key="EditorConfiguration.AutoSpacesForTabs">false</value>
+ <value type="bool" key="EditorConfiguration.CamelCaseNavigation">true</value>
+ <valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.0">
+ <value type="QString" key="language">Cpp</value>
+ <valuemap type="QVariantMap" key="value">
+ <value type="QByteArray" key="CurrentPreferences">qt2</value>
+ </valuemap>
+ </valuemap>
+ <valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.1">
+ <value type="QString" key="language">QmlJS</value>
+ <valuemap type="QVariantMap" key="value">
+ <value type="QByteArray" key="CurrentPreferences">QmlJSGlobal</value>
+ </valuemap>
+ </valuemap>
+ <value type="int" key="EditorConfiguration.CodeStyle.Count">2</value>
+ <value type="QByteArray" key="EditorConfiguration.Codec">UTF-8</value>
+ <value type="bool" key="EditorConfiguration.ConstrainTooltips">false</value>
+ <value type="int" key="EditorConfiguration.IndentSize">2</value>
+ <value type="bool" key="EditorConfiguration.KeyboardTooltips">false</value>
+ <value type="int" key="EditorConfiguration.MarginColumn">80</value>
+ <value type="bool" key="EditorConfiguration.MouseHiding">true</value>
+ <value type="bool" key="EditorConfiguration.MouseNavigation">true</value>
+ <value type="int" key="EditorConfiguration.PaddingMode">1</value>
+ <value type="bool" key="EditorConfiguration.ScrollWheelZooming">true</value>
+ <value type="bool" key="EditorConfiguration.ShowMargin">false</value>
+ <value type="int" key="EditorConfiguration.SmartBackspaceBehavior">0</value>
+ <value type="bool" key="EditorConfiguration.SmartSelectionChanging">true</value>
+ <value type="bool" key="EditorConfiguration.SpacesForTabs">true</value>
+ <value type="int" key="EditorConfiguration.TabKeyBehavior">0</value>
+ <value type="int" key="EditorConfiguration.TabSize">4</value>
+ <value type="bool" key="EditorConfiguration.UseGlobal">false</value>
+ <value type="int" key="EditorConfiguration.Utf8BomBehavior">1</value>
+ <value type="bool" key="EditorConfiguration.addFinalNewLine">true</value>
+ <value type="bool" key="EditorConfiguration.cleanIndentation">true</value>
+ <value type="bool" key="EditorConfiguration.cleanWhitespace">false</value>
+ <value type="bool" key="EditorConfiguration.inEntireDocument">false</value>
+ </valuemap>
+ </data>
+ <data>
+ <variable>ProjectExplorer.Project.PluginSettings</variable>
+ <valuemap type="QVariantMap"/>
+ </data>
+ <data>
+ <variable>ProjectExplorer.Project.Target.0</variable>
+ <valuemap type="QVariantMap">
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Desktop</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Desktop</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{ed04208c-8774-456b-99b9-4a02094ca7a4}</value>
+ <value type="int" key="ProjectExplorer.Target.ActiveBuildConfiguration">0</value>
+ <value type="int" key="ProjectExplorer.Target.ActiveDeployConfiguration">0</value>
+ <value type="int" key="ProjectExplorer.Target.ActiveRunConfiguration">0</value>
+ <valuemap type="QVariantMap" key="ProjectExplorer.Target.BuildConfiguration.0">
+ <value type="QString" key="ProjectExplorer.BuildConfiguration.BuildDirectory">/home/sdomas/Projet/Blast/code/blast</value>
+ <valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0">
+ <valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0">
+ <valuelist type="QVariantList" key="GenericProjectManager.GenericMakeStep.BuildTargets">
+ <value type="QString">all</value>
+ </valuelist>
+ <value type="bool" key="GenericProjectManager.GenericMakeStep.Clean">false</value>
+ <value type="QString" key="GenericProjectManager.GenericMakeStep.MakeArguments"></value>
+ <value type="QString" key="GenericProjectManager.GenericMakeStep.MakeCommand"></value>
+ <value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericMakeStep</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Compiler</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Build</value>
+ </valuemap>
+ <valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.1">
+ <valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0">
+ <valuelist type="QVariantList" key="GenericProjectManager.GenericMakeStep.BuildTargets">
+ <value type="QString">clean</value>
+ </valuelist>
+ <value type="bool" key="GenericProjectManager.GenericMakeStep.Clean">true</value>
+ <value type="QString" key="GenericProjectManager.GenericMakeStep.MakeArguments"></value>
+ <value type="QString" key="GenericProjectManager.GenericMakeStep.MakeCommand"></value>
+ <value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericMakeStep</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Nettoyer</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Clean</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">2</value>
+ <value type="bool" key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment">false</value>
+ <valuelist type="QVariantList" key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges"/>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Défaut</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Défaut</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericBuildConfiguration</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.Target.BuildConfigurationCount">1</value>
+ <valuemap type="QVariantMap" key="ProjectExplorer.Target.DeployConfiguration.0">
+ <valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0">
+ <value type="int" key="ProjectExplorer.BuildStepList.StepsCount">0</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Déploiement</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Deploy</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">1</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Déployer localement</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.DefaultDeployConfiguration</value>
+ </valuemap>
+ <value type="int" key="ProjectExplorer.Target.DeployConfigurationCount">1</value>
+ <valuemap type="QVariantMap" key="ProjectExplorer.Target.PluginSettings"/>
+ <valuemap type="QVariantMap" key="ProjectExplorer.Target.RunConfiguration.0">
+ <value type="bool" key="Analyzer.QmlProfiler.AggregateTraces">false</value>
+ <value type="bool" key="Analyzer.QmlProfiler.FlushEnabled">false</value>
+ <value type="uint" key="Analyzer.QmlProfiler.FlushInterval">0</value>
+ <value type="QString" key="Analyzer.QmlProfiler.LastTraceFile"></value>
+ <value type="bool" key="Analyzer.QmlProfiler.Settings.UseGlobalSettings">true</value>
+ <valuelist type="QVariantList" key="Analyzer.Valgrind.AddedSuppressionFiles"/>
+ <value type="bool" key="Analyzer.Valgrind.Callgrind.CollectBusEvents">false</value>
+ <value type="bool" key="Analyzer.Valgrind.Callgrind.CollectSystime">false</value>
+ <value type="bool" key="Analyzer.Valgrind.Callgrind.EnableBranchSim">false</value>
+ <value type="bool" key="Analyzer.Valgrind.Callgrind.EnableCacheSim">false</value>
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+ <value type="int">12</value>
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+ </valuelist>
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+ <value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.WorkingDirectory">%{buildDir}</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Exécutable personnalisé</value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
+ <value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.CustomExecutableRunConfiguration</value>
+ <value type="uint" key="RunConfiguration.QmlDebugServerPort">3768</value>
+ <value type="bool" key="RunConfiguration.UseCppDebugger">false</value>
+ <value type="bool" key="RunConfiguration.UseCppDebuggerAuto">true</value>
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+ <data>
+ <variable>ProjectExplorer.Project.TargetCount</variable>
+ <value type="int">1</value>
+ </data>
+ <data>
+ <variable>ProjectExplorer.Project.Updater.FileVersion</variable>
+ <value type="int">18</value>
+ </data>
+ <data>
+ <variable>Version</variable>
+ <value type="int">18</value>
+ </data>
+</qtcreator>
Exception.h
Exception.cpp
+AbstractInputModifier.h
+AbstractInputModifier.cpp
+DelayInputModifier.h
+DelayInputModifier.cpp
AbstractBlock.h
AbstractBlock.cpp
AbstractBoxItem.h
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<config>
- <categories nb="9">
+ <categories>
<category name="root" id="0" parent="-1"/>
<category name="math" id="1" parent="0"/>
<category name="trigonemetric" id="2" parent="1"/>
<category name="wishbone" id="5" parent="0"/>
<category name="generators" id="6" parent="0"/>
<category name="observers" id="7" parent="0"/>
- <category name="user" id="8" parent="0"/>
+ <category name="user" id="8" parent="0"/>
+ <category name="unclassified" id="99" parent="0"/>
</categories>
<references nb="2" lib_file="/home/sdomas/Projet/Blast/code/blast/lib/references/references.bmf" >
<xs:sequence>
<xs:element ref="category" maxOccurs="unbounded" />
</xs:sequence>
- <xs:attribute ref="nb" use="required"/>
</xs:complexType>
</xs:element>
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : boxfilter_3x3.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a box (i.e. average) filter with a 3x3 mask
+-- on a grayscale image. The width of the image must be <= 1024.
+-- Image size must be provided via generics
+--
+-- Note :
+-- CP = 1{$img_width*$img_height}
+-- PP = 0{$img_width+7}1{$img_width*$img_height}
+-- PC = {$img_width+2:$img_width*$img_height-($img_width+2):1},{$img_width*$img_height:$img_width+2,0}
+-- delta = $img_width*$img_height
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity boxfilter_3x3 is
+ generic(
+ img_width : natural := 128;
+ img_height : natural := 128;
+ dsp_in_width : natural := 18;
+ dsp_out_width : natural := 36
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ pix_in : in std_logic_vector(7 downto 0);
+ pix_in_enb : in std_logic;
+ pix_out : out std_logic_vector(7 downto 0);
+ pix_out_enb : out std_logic
+ );
+end boxfilter_3x3;
+
+
+architecture rtl of boxfilter_3x3 is
+
+ component ram_dp_1024x8
+ port (
+ clka : in std_logic;
+ wea : in std_logic_vector(0 downto 0);
+ addra : in std_logic_vector(9 downto 0);
+ dina : in std_logic_vector(7 downto 0);
+ douta : out std_logic_vector(7 downto 0);
+ clkb : in std_logic;
+ web : in std_logic_vector(0 downto 0);
+ addrb : in std_logic_vector(9 downto 0);
+ dinb : in std_logic_vector(7 downto 0);
+ doutb : out std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ -- Signals
+
+ -- constant signal set tup to img limits
+ signal count_col_end : unsigned (9 downto 0);
+ signal count_row_end : unsigned (9 downto 0);
+
+ -- for storing image rows
+ signal sel_mem : unsigned (1 downto 0); -- the current memorize row
+ signal wea_0 : std_logic_vector(0 downto 0); -- we for memorized row 0
+ signal wea_1 : std_logic_vector(0 downto 0); -- we for memorized row 1
+ signal wea_2 : std_logic_vector(0 downto 0); -- we for memorized row 2
+
+ signal dina_0 : std_logic_vector(7 downto 0);
+ signal dina_1 : std_logic_vector(7 downto 0);
+ signal dina_2 : std_logic_vector(7 downto 0);
+ signal dina : std_logic_vector(7 downto 0);
+
+ signal addra_w : std_logic_vector(9 downto 0);
+ signal addra_w_s : unsigned (9 downto 0);
+ signal wea : std_logic;
+
+
+ signal addrb_r : std_logic_vector(9 downto 0); -- addr where to store
+ signal addrb_r_s : unsigned (9 downto 0); -- addr where to store
+
+ signal doutb_0 : std_logic_vector(7 downto 0);
+ signal doutb_1 : std_logic_vector(7 downto 0);
+ signal doutb_2 : std_logic_vector(7 downto 0);
+
+ signal count_row_w : unsigned (10 downto 0); -- row counter while storing
+ signal store_last_pix : std_logic; -- to be sure that last pixel is stored
+ signal first_row_w : std_logic; -- '1' when the first row is read so that
+ -- mem_0 is filled with zeroes
+ signal all_pix_stored : std_logic; -- '1' when all pixels have been stored
+
+ -- for reading image rows
+ signal start_read : std_logic;
+ signal do_read : std_logic;
+ signal count_row_r : unsigned (10 downto 0);
+ signal count_row_r_dly : unsigned (10 downto 0);
+ signal wea_dly : std_logic;
+ signal end_read : std_logic;
+
+ -- for doing sums
+ signal do_sum : std_logic;
+ signal sum1 : unsigned (9 downto 0);
+ signal sum2 : unsigned (9 downto 0);
+ signal sum3 : unsigned (9 downto 0);
+
+ -- for doing total
+ signal do_total : std_logic;
+ signal sum : unsigned (dsp_in_width-1 downto 0);
+ signal count_col_total : unsigned (10 downto 0);
+ signal count_row_total : unsigned (10 downto 0);
+ signal jump_first_sum : std_logic;
+
+ -- for doing final division
+ signal do_div : std_logic;
+ signal do_out : std_logic;
+ signal end_filter : std_logic;
+ signal cst_mult : unsigned(dsp_in_width-1 downto 0); -- eq. 14564 (=2^17/9)
+ signal mult_result : unsigned (dsp_out_width-1 downto 0);
+
+
+begin
+
+ img_row_0 : ram_dp_1024x8
+ port map (
+ clka => clk,
+ wea => wea_0,
+ addra => addra_w,
+ dina => dina_0,
+ clkb => clk,
+ web => (others => '0'),
+ addrb => addrb_r,
+ dinb => (others => '0'),
+ doutb => doutb_0
+ );
+ img_row_1 : ram_dp_1024x8
+ port map (
+ clka => clk,
+ wea => wea_1,
+ addra => addra_w,
+ dina => dina_1,
+ clkb => clk,
+ web => (others => '0'),
+ addrb => addrb_r,
+ dinb => (others => '0'),
+ doutb => doutb_1
+ );
+ img_row_2 : ram_dp_1024x8
+ port map (
+ clka => clk,
+ wea => wea_2,
+ addra => addra_w,
+ dina => dina_2,
+ clkb => clk,
+ web => (others => '0'),
+ addrb => addrb_r,
+ dinb => (others => '0'),
+ doutb => doutb_2
+ );
+
+
+ cst_mult <= to_unsigned(14564, dsp_in_width);
+ count_col_end <= to_unsigned(img_width-1, 10);
+ count_row_end <= to_unsigned(img_height-1, 10);
+
+ addra_w <= std_logic_vector(addra_w_s);
+ addrb_r <= std_logic_vector(addrb_r_s);
+
+ wea_0 <= "1" when ((sel_mem = 0 or first_row_w = '1') and wea = '1') else
+ "0";
+ wea_1 <= "1" when (sel_mem = 1 and wea = '1') else
+ "0";
+ wea_2 <= "1" when (sel_mem = 2 and wea = '1') else
+ "0";
+
+ dina_0 <= (others => '0') when (first_row_w = '1') else
+ dina;
+
+ dina_1 <= dina;
+ dina_2 <= dina;
+
+ store_row_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ sel_mem <= to_unsigned(0, 2);
+ addra_w_s <= to_unsigned(img_width-1, 10);
+ dina <= (others => '0');
+
+ wea <= '0';
+ count_row_w <= to_unsigned(0, 11);
+
+ start_read <= '0';
+ first_row_w <= '1';
+ store_last_pix <= '0';
+ all_pix_stored <= '0';
+
+ elsif rising_edge(clk) then
+
+ wea <= '0';
+ start_read <= '0';
+ dina <= (others => '0');
+ store_last_pix <= '0';
+
+ -- reset all when filter has ended
+ if end_filter = '1' then
+
+ count_row_w <= to_unsigned(0, 11);
+ sel_mem <= to_unsigned(0, 2);
+ addra_w_s <= to_unsigned(img_width-1, 10);
+ first_row_w <= '1';
+ all_pix_stored <= '0';
+
+ elsif store_last_pix = '1' then
+ addra_w_s <= to_unsigned(0, 10);
+ -- select next ram
+ if sel_mem = 2 then
+ sel_mem <= to_unsigned(0, 2);
+ else
+ sel_mem <= sel_mem + 1;
+ end if;
+ all_pix_stored <= '1'; -- all pixels are stored
+
+ elsif pix_in_enb = '1' then
+
+ -- prepare to write
+ wea <= '1';
+ -- take input
+ dina <= pix_in;
+ -- check if this is the last pixel
+ if addra_w_s = img_width-2 and count_row_w = img_height then
+ store_last_pix <= '1';
+ end if;
+ -- if at line end
+ if addra_w_s = img_width-1 then
+ -- back to 0
+ addra_w_s <= to_unsigned(0, 10);
+ -- select next ram
+ if sel_mem = 2 then
+ sel_mem <= to_unsigned(0, 2);
+ else
+ sel_mem <= sel_mem + 1;
+ end if;
+ -- end of first line to store
+ if count_row_w = 1 then
+ first_row_w <= '0';
+ start_read <= '1';
+ end if;
+ count_row_w <= count_row_w + 1;
+ else
+ addra_w_s <= addra_w_s + 1;
+ end if;
+ end if;
+ end if;
+
+ end process store_row_process;
+
+ read_rows_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ addrb_r_s <= to_unsigned(0, 10);
+ do_read <= '0';
+ wea_dly <= '0';
+
+ count_row_r <= to_unsigned(0, 11);
+ end_read <= '0';
+
+ do_sum <= '0';
+
+ elsif rising_edge(clk) then
+
+ wea_dly <= wea;
+ do_sum <= '0';
+ end_read <= '0';
+
+ if end_read = '1' then
+ do_sum <= '1';
+ end if;
+
+ if start_read = '1' then
+ do_read <= '1';
+
+ elsif do_read = '1' and (all_pix_stored = '1' or wea_dly = '1') then
+
+ do_sum <= '1';
+ -- whatever the case inc addr if not at end
+ if addrb_r_s = img_width-1 then
+ addrb_r_s <= to_unsigned(0, 10);
+ if count_row_r = img_height-1 then
+ count_row_r <= to_unsigned(0, 11);
+ do_read <= '0';
+ end_read <= '1';
+ else
+ count_row_r <= count_row_r+1;
+ end if;
+ else
+ addrb_r_s <= addrb_r_s + 1;
+ end if;
+ end if;
+ end if;
+
+ end process read_rows_process;
+
+ sum_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ sum1 <= to_unsigned(0, 10);
+ sum2 <= to_unsigned(0, 10);
+ sum3 <= to_unsigned(0, 10);
+ count_row_r_dly <= to_unsigned(0, 11);
+ do_total <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_total <= '0';
+ count_row_r_dly <= count_row_r;
+
+ if end_filter = '1' then
+ sum1 <= to_unsigned(0, 10);
+ sum2 <= to_unsigned(0, 10);
+ sum3 <= to_unsigned(0, 10);
+ end if;
+ if do_sum = '1' then
+
+ sum3 <= sum2;
+ sum2 <= sum1;
+ if count_row_r_dly = img_height-1 then
+ if sel_mem = 0 then
+ sum1 <= unsigned("00" & doutb_1) + unsigned("00" & doutb_2);
+ elsif sel_mem = 1 then
+ sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_2);
+ elsif sel_mem = 2 then
+ sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_1);
+ end if;
+ else
+ sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_1) + unsigned("00" & doutb_2);
+ end if;
+ do_total <= '1';
+ end if;
+ end if;
+
+ end process sum_process;
+
+ total_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ sum <= to_unsigned(0, dsp_in_width);
+
+ jump_first_sum <= '0';
+ count_row_total <= to_unsigned(0, 11);
+ count_col_total <= to_unsigned(0, 11);
+ do_div <= '0';
+ end_filter <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_div <= '0';
+ end_filter <= '0';
+
+ if do_total = '1' then
+
+ if jump_first_sum = '1' then
+ -- sum for the end of the line
+ if count_col_total = img_width-1 then
+ sum <= resize(sum2, dsp_in_width) + resize(sum3, dsp_in_width);
+ count_col_total <= to_unsigned(0, 11);
+ if count_row_total = img_height-1 then
+ end_filter <= '1';
+ count_row_total <= to_unsigned(0, 11);
+ jump_first_sum <= '0';
+ else
+ count_row_total <= count_row_total + 1;
+ end if;
+ -- sum for the begining of the line
+ elsif count_col_total = 0 then
+ sum <= resize(sum1, dsp_in_width) + resize(sum2, dsp_in_width);
+ count_col_total <= to_unsigned(1, 11);
+ else
+ sum <= resize(sum1, dsp_in_width) + resize(sum2, dsp_in_width) + resize(sum3, dsp_in_width);
+ count_col_total <= count_col_total + 1;
+ end if;
+ do_div <= '1';
+ else
+ jump_first_sum <= '1';
+ end if;
+ end if;
+
+
+ end if;
+
+ end process total_process;
+
+ final_div_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ mult_result <= to_unsigned(0, dsp_out_width);
+ do_out <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_out <= '0';
+
+ if do_div = '1' then
+ mult_result <= sum * cst_mult;
+ do_out <= '1';
+ end if;
+ end if;
+ end process final_div_process;
+
+ pix_out <= std_logic_vector(mult_result(24 downto 17));
+ pix_out_enb <= do_out;
+
+end rtl;
+
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : checker.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a threshold on an input
+--
+--
+-- Note : The input is compared to one (or two) values and depending
+-- on the result and the type of the comparison, the check output
+-- is asserted to 1 or not.
+-- The values are fixed by generic parameter.
+-- The type of check is fixed by a generic paramter
+-- type 1 : test if lesser or equal than X
+-- type 2 : test if gretar or equal than X
+-- type 3 : test if greater or equal than X and lesser or equal than Y
+--
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity checker is
+ generic(
+ in_width : natural := 8;
+ check_type : natural := 1;
+ inf_value : natural := 0;
+ sup_value : natural := 0
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(in_width-1 downto 0);
+ data_in_enb : in std_logic;
+ data_out : out std_logic_vector(in_width-1 downto 0);
+ data_out_enb : out std_logic;
+ check_out : out std_logic;
+ check_out_enb : out std_logic
+ );
+end checker;
+
+
+architecture rtl of checker is
+
+begin
+
+ check_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ check_out <= '0';
+ data_out <= (others => '0');
+ data_out_enb <= '0';
+ check_out_enb <= '0';
+
+ elsif rising_edge(clk) then
+
+ check_out <= '0';
+ data_out <= (others => '0');
+ data_out_enb <= '0';
+ check_out_enb <= '0';
+
+ if data_in_enb = '1' then
+
+ data_out <= data_in;
+ data_out_enb <= '1';
+ check_out_enb <= '1';
+
+ if check_type = 1 then
+ if unsigned(data_in) <= inf_value then
+ check_out <= '1';
+ end if;
+ elsif check_type = 2 then
+ if unsigned(data_in) >= inf_value then
+ check_out <= '1';
+ end if;
+ elsif check_type = 3 then
+ if unsigned(data_in) >= inf_value and unsigned(data_in) <= sup_value then
+ check_out <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+
+ end process check_process;
+
+end rtl;
+
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : deserializer_3x1.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a deserialization of 3 element into
+-- 3 parallel outputs
+--
+--
+-- Note :
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity deserializer_3x1 is
+ generic(
+ in_width : natural := 8
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(in_width-1 downto 0);
+ data_in_enb : in std_logic;
+ data1_out : out std_logic_vector(in_width-1 downto 0);
+ data1_out_enb : out std_logic;
+ data2_out : out std_logic_vector(in_width-1 downto 0);
+ data2_out_enb : out std_logic;
+ data3_out : out std_logic_vector(in_width-1 downto 0);
+ data3_out_enb : out std_logic
+
+ );
+end deserializer_3x1;
+
+
+architecture rtl of deserializer_3x1 is
+
+ -- Signals
+ signal do_out : std_logic;
+ signal data1_reg : std_logic_vector(in_width-1 downto 0);
+ signal data2_reg : std_logic_vector(in_width-1 downto 0);
+
+ signal count : unsigned(1 downto 0);
+
+begin
+
+ deser_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ count <= to_unsigned(0, 2);
+ data1_reg <= (others => '0');
+ data2_reg <= (others => '0');
+ data1_out <= (others => '0');
+ data2_out <= (others => '0');
+ data3_out <= (others => '0');
+ do_out <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_out <= '0';
+ data1_out <= (others => '0');
+ data2_out <= (others => '0');
+ data3_out <= (others => '0');
+
+ if data_in_enb = '1' then
+
+ if count = 0 then
+ data1_reg <= data_in;
+ count <= count + 1;
+ elsif count = 1 then
+ data2_reg <= data_in;
+ count <= count + 1;
+ elsif count = 2 then
+ data1_out <= data1_reg;
+ data2_out <= data2_reg;
+ data3_out <= data_in;
+ do_out <= '1';
+ count <= to_unsigned(0, 2);
+ end if;
+ end if;
+ end if;
+
+ end process deser_process;
+
+ data1_out_enb <= do_out;
+ data2_out_enb <= do_out;
+ data3_out_enb <= do_out;
+
+end rtl;
+
--- /dev/null
+<!DOCTYPE boxfilter_3x3>
+<block_impl ref_name="boxfilter_3x3.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>frdfgdr</description>
+ <notes>gregre</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+component ram_dp_1024x8
+port (
+clka : in std_logic;
+wea : in std_logic_vector(0 downto 0);
+addra : in std_logic_vector(9 downto 0);
+dina : in std_logic_vector(7 downto 0);
+douta : out std_logic_vector(7 downto 0);
+clkb : in std_logic;
+web : in std_logic_vector(0 downto 0);
+addrb : in std_logic_vector(9 downto 0);
+dinb : in std_logic_vector(7 downto 0);
+doutb : out std_logic_vector(7 downto 0)
+);
+end component;
+
+-- Signals
+
+-- constant signal set tup to img limits
+signal count_col_end : unsigned (9 downto 0);
+signal count_row_end : unsigned (9 downto 0);
+
+-- for storing image rows
+signal sel_mem : unsigned (1 downto 0); -- the current memorize row
+signal wea_0 : std_logic_vector(0 downto 0); -- we for memorized row 0
+signal wea_1 : std_logic_vector(0 downto 0); -- we for memorized row 1
+signal wea_2 : std_logic_vector(0 downto 0); -- we for memorized row 2
+
+signal dina_0 : std_logic_vector(7 downto 0);
+signal dina_1 : std_logic_vector(7 downto 0);
+signal dina_2 : std_logic_vector(7 downto 0);
+signal dina : std_logic_vector(7 downto 0);
+
+signal addra_w : std_logic_vector(9 downto 0);
+signal addra_w_s : unsigned (9 downto 0);
+signal wea : std_logic;
+
+
+signal addrb_r : std_logic_vector(9 downto 0); -- addr where to store
+signal addrb_r_s : unsigned (9 downto 0); -- addr where to store
+
+signal doutb_0 : std_logic_vector(7 downto 0);
+signal doutb_1 : std_logic_vector(7 downto 0);
+signal doutb_2 : std_logic_vector(7 downto 0);
+
+signal count_row_w : unsigned (10 downto 0); -- row counter while storing
+signal store_last_pix : std_logic; -- to be sure that last pixel is stored
+signal first_row_w : std_logic; -- '1' when the first row is read so that
+-- mem_0 is filled with zeroes
+signal all_pix_stored : std_logic; -- '1' when all pixels have been stored
+
+-- for reading image rows
+signal start_read : std_logic;
+signal do_read : std_logic;
+signal count_row_r : unsigned (10 downto 0);
+signal count_row_r_dly : unsigned (10 downto 0);
+signal wea_dly : std_logic;
+signal end_read : std_logic;
+
+-- for doing sums
+signal do_sum : std_logic;
+signal sum1 : unsigned (9 downto 0);
+signal sum2 : unsigned (9 downto 0);
+signal sum3 : unsigned (9 downto 0);
+
+-- for doing total
+signal do_total : std_logic;
+signal sum : unsigned (dsp_in_width-1 downto 0);
+signal count_col_total : unsigned (10 downto 0);
+signal count_row_total : unsigned (10 downto 0);
+signal jump_first_sum : std_logic;
+
+-- for doing final division
+signal do_div : std_logic;
+signal do_out : std_logic;
+signal end_filter : std_logic;
+signal cst_mult : unsigned(dsp_in_width-1 downto 0); -- eq. 14564 (=2^17/9)
+signal mult_result : unsigned (dsp_out_width-1 downto 0);
+
+
+begin
+
+img_row_0 : ram_dp_1024x8
+port map (
+clka => @{clk},
+wea => wea_0,
+addra => addra_w,
+dina => dina_0,
+clkb => @{clk},
+web => (others => '0'),
+addrb => addrb_r,
+dinb => (others => '0'),
+doutb => doutb_0
+);
+img_row_1 : ram_dp_1024x8
+port map (
+clka => @{clk},
+wea => wea_1,
+addra => addra_w,
+dina => dina_1,
+clkb => @{clk},
+web => (others => '0'),
+addrb => addrb_r,
+dinb => (others => '0'),
+doutb => doutb_1
+);
+img_row_2 : ram_dp_1024x8
+port map (
+clka => @{clk},
+wea => wea_2,
+addra => addra_w,
+dina => dina_2,
+clkb => @{clk},
+web => (others => '0'),
+addrb => addrb_r,
+dinb => (others => '0'),
+doutb => doutb_2
+);
+
+
+cst_mult <= to_unsigned(14564, dsp_in_width);
+count_col_end <= to_unsigned(img_width-1, 10);
+count_row_end <= to_unsigned(img_height-1, 10);
+
+addra_w <= std_logic_vector(addra_w_s);
+addrb_r <= std_logic_vector(addrb_r_s);
+
+wea_0 <= "1" when ((sel_mem = 0 or first_row_w = '1') and wea = '1') else
+"0";
+wea_1 <= "1" when (sel_mem = 1 and wea = '1') else
+"0";
+wea_2 <= "1" when (sel_mem = 2 and wea = '1') else
+"0";
+
+dina_0 <= (others => '0') when (first_row_w = '1') else
+dina;
+
+dina_1 <= dina;
+dina_2 <= dina;
+
+store_row_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+sel_mem <= to_unsigned(0, 2);
+addra_w_s <= to_unsigned(img_width-1, 10);
+dina <= (others => '0');
+
+wea <= '0';
+count_row_w <= to_unsigned(0, 11);
+
+start_read <= '0';
+first_row_w <= '1';
+store_last_pix <= '0';
+all_pix_stored <= '0';
+
+elsif rising_edge(@{clk}) then
+
+wea <= '0';
+start_read <= '0';
+dina <= (others => '0');
+store_last_pix <= '0';
+
+-- @{reset} all when filter has ended
+if end_filter = '1' then
+
+count_row_w <= to_unsigned(0, 11);
+sel_mem <= to_unsigned(0, 2);
+addra_w_s <= to_unsigned(img_width-1, 10);
+first_row_w <= '1';
+all_pix_stored <= '0';
+
+elsif store_last_pix = '1' then
+addra_w_s <= to_unsigned(0, 10);
+-- select next ram
+if sel_mem = 2 then
+sel_mem <= to_unsigned(0, 2);
+else
+sel_mem <= sel_mem + 1;
+end if;
+all_pix_stored <= '1'; -- all pixels are stored
+
+elsif @{pix_in_enb} = '1' then
+
+-- prepare to write
+wea <= '1';
+-- take input
+dina <= @{pix_in};
+-- check if this is the last pixel
+if addra_w_s = img_width-2 and count_row_w = img_height then
+store_last_pix <= '1';
+end if;
+-- if at line end
+if addra_w_s = img_width-1 then
+-- back to 0
+addra_w_s <= to_unsigned(0, 10);
+-- select next ram
+if sel_mem = 2 then
+sel_mem <= to_unsigned(0, 2);
+else
+sel_mem <= sel_mem + 1;
+end if;
+-- end of first line to store
+if count_row_w = 1 then
+first_row_w <= '0';
+start_read <= '1';
+end if;
+count_row_w <= count_row_w + 1;
+else
+addra_w_s <= addra_w_s + 1;
+end if;
+end if;
+end if;
+
+end process store_row_process;
+
+read_rows_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+addrb_r_s <= to_unsigned(0, 10);
+do_read <= '0';
+wea_dly <= '0';
+
+count_row_r <= to_unsigned(0, 11);
+end_read <= '0';
+
+do_sum <= '0';
+
+elsif rising_edge(@{clk}) then
+
+wea_dly <= wea;
+do_sum <= '0';
+end_read <= '0';
+
+if end_read = '1' then
+do_sum <= '1';
+end if;
+
+if start_read = '1' then
+do_read <= '1';
+
+elsif do_read = '1' and (all_pix_stored = '1' or wea_dly = '1') then
+
+do_sum <= '1';
+-- whatever the case inc addr if not at end
+if addrb_r_s = img_width-1 then
+addrb_r_s <= to_unsigned(0, 10);
+if count_row_r = img_height-1 then
+count_row_r <= to_unsigned(0, 11);
+do_read <= '0';
+end_read <= '1';
+else
+count_row_r <= count_row_r+1;
+end if;
+else
+addrb_r_s <= addrb_r_s + 1;
+end if;
+end if;
+end if;
+
+end process read_rows_process;
+
+sum_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+sum1 <= to_unsigned(0, 10);
+sum2 <= to_unsigned(0, 10);
+sum3 <= to_unsigned(0, 10);
+count_row_r_dly <= to_unsigned(0, 11);
+do_total <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_total <= '0';
+count_row_r_dly <= count_row_r;
+
+if end_filter = '1' then
+sum1 <= to_unsigned(0, 10);
+sum2 <= to_unsigned(0, 10);
+sum3 <= to_unsigned(0, 10);
+end if;
+if do_sum = '1' then
+
+sum3 <= sum2;
+sum2 <= sum1;
+if count_row_r_dly = img_height-1 then
+if sel_mem = 0 then
+sum1 <= unsigned("00" & doutb_1) + unsigned("00" & doutb_2);
+elsif sel_mem = 1 then
+sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_2);
+elsif sel_mem = 2 then
+sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_1);
+end if;
+else
+sum1 <= unsigned("00" & doutb_0) + unsigned("00" & doutb_1) + unsigned("00" & doutb_2);
+end if;
+do_total <= '1';
+end if;
+end if;
+
+end process sum_process;
+
+total_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+sum <= to_unsigned(0, dsp_in_width);
+
+jump_first_sum <= '0';
+count_row_total <= to_unsigned(0, 11);
+count_col_total <= to_unsigned(0, 11);
+do_div <= '0';
+end_filter <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_div <= '0';
+end_filter <= '0';
+
+if do_total = '1' then
+
+if jump_first_sum = '1' then
+-- sum for the end of the line
+if count_col_total = img_width-1 then
+sum <= resize(sum2, dsp_in_width) + resize(sum3, dsp_in_width);
+count_col_total <= to_unsigned(0, 11);
+if count_row_total = img_height-1 then
+end_filter <= '1';
+count_row_total <= to_unsigned(0, 11);
+jump_first_sum <= '0';
+else
+count_row_total <= count_row_total + 1;
+end if;
+-- sum for the begining of the line
+elsif count_col_total = 0 then
+sum <= resize(sum1, dsp_in_width) + resize(sum2, dsp_in_width);
+count_col_total <= to_unsigned(1, 11);
+else
+sum <= resize(sum1, dsp_in_width) + resize(sum2, dsp_in_width) + resize(sum3, dsp_in_width);
+count_col_total <= count_col_total + 1;
+end if;
+do_div <= '1';
+else
+jump_first_sum <= '1';
+end if;
+end if;
+
+
+end if;
+
+end process total_process;
+
+final_div_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+mult_result <= to_unsigned(0, dsp_out_width);
+do_out <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_out <= '0';
+
+if do_div = '1' then
+mult_result <= sum * cst_mult;
+do_out <= '1';
+end if;
+end if;
+end process final_div_process;
+
+@{pix_out} <= std_logic_vector(mult_result(24 downto 17));
+@{pix_out_enb} <= do_out;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="$img_width*$img_height"/>
+ <consumption>
+ <input pattern="1{$img_width*$img_height}" name="pix_in_enb"/>
+ </consumption>
+ <production counter="{$img_width+2:$img_width*$img_height-($img_width+2):1},{$img_width*$img_height:$img_width+2:0}">
+ <output pattern="0{$img_width+7}1{$img_width*$img_height}" name="pix_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<!DOCTYPE checker>
+<block_impl ref_name="checker.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>frdfgdr</description>
+ <notes>gre</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+begin
+
+check_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+@{check_out} <= '0';
+@{data_out} <= (others => '0');
+@{data_out_enb} <= '0';
+@{check_out_enb} <= '0';
+
+elsif rising_edge(@{clk}) then
+
+@{check_out} <= '0';
+@{data_out} <= (others => '0');
+@{data_out_enb} <= '0';
+@{check_out_enb} <= '0';
+
+if @{data_in_enb} = '1' then
+
+@{data_out} <= @{data_in};
+@{data_out_enb} <= '1';
+@{check_out_enb} <= '1';
+
+if check_type = 1 then
+if unsigned(@{data_in}) <= inf_value then
+@{check_out} <= '1';
+end if;
+elsif check_type = 2 then
+if unsigned(@{data_in}) >= inf_value then
+@{check_out} <= '1';
+end if;
+elsif check_type = 3 then
+if unsigned(@{data_in}) >= inf_value and unsigned(@{data_in}) <= sup_value then
+@{check_out} <= '1';
+end if;
+end if;
+end if;
+end if;
+
+end process check_process;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="1"/>
+ <consumption>
+ <input pattern="1" name="data_in_enb"/>
+ </consumption>
+ <production counter="1">
+ <output pattern="01" name="data_out_enb"/>
+ <output pattern="01" name="check_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<block_impl ref_name="csvreader.xml" ref_md5="">
+ <comments>
+ <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
+ <date creation="2015-05-10" />
+ <related_files list=""/>
+ <description>
+ This component read data in a CSV file
+ </description>
+ <notes>
+ No notes
+ </notes>
+ </comments>
+
+ <libraries>
+ <library name="IEEE">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+
+ <architecture>
+
+ </architecture>
+
+ <patterns>
+ <delta value="$row_length*$nb_row" />
+ <consumption>
+ </consumption>
+ <production counter="1">
+ <output name="data_out_enb" pattern="$out_pattern" />
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<!DOCTYPE deserializer_3x1>
+<block_impl ref_name="deserializer_3x1.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>gre</description>
+ <notes>gre</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+-- Signals
+signal do_out : std_logic;
+signal data1_reg : std_logic_vector(in_width-1 downto 0);
+signal data2_reg : std_logic_vector(in_width-1 downto 0);
+
+signal count : unsigned(1 downto 0);
+
+begin
+
+deser_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+count <= to_unsigned(0, 2);
+data1_reg <= (others => '0');
+data2_reg <= (others => '0');
+@{data1_out} <= (others => '0');
+@{data2_out} <= (others => '0');
+@{data3_out} <= (others => '0');
+do_out <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_out <= '0';
+@{data1_out} <= (others => '0');
+@{data2_out} <= (others => '0');
+@{data3_out} <= (others => '0');
+
+if @{data_in_enb} = '1' then
+
+if count = 0 then
+data1_reg <= @{data_in};
+count <= count + 1;
+elsif count = 1 then
+data2_reg <= @{data_in};
+count <= count + 1;
+elsif count = 2 then
+@{data1_out} <= data1_reg;
+@{data2_out} <= data2_reg;
+@{data3_out} <= @{data_in};
+do_out <= '1';
+count <= to_unsigned(0, 2);
+end if;
+end if;
+end if;
+
+end process deser_process;
+
+@{data1_out_enb} <= do_out;
+@{data2_out_enb} <= do_out;
+@{data3_out_enb} <= do_out;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="3"/>
+ <consumption>
+ <input pattern="111" name="data_in_enb"/>
+ </consumption>
+ <production counter="3">
+ <output pattern="0001" name="data1_out_enb"/>
+ <output pattern="0001" name="data2_out_enb"/>
+ <output pattern="0001" name="data3_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<!DOCTYPE logical_AND_3>
+<block_impl ref_name="logical_AND_3.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>yt</description>
+ <notes>hyjt</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+begin
+
+and_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+@{data_out} <= '0';
+@{data_out_enb} <= '0';
+
+elsif rising_edge(@{clk}) then
+
+@{data_out} <= '0';
+@{data_out_enb} <= '0';
+
+if @{data1_in_enb} = '1' and @{data2_in_enb} = '1' and @{data3_in_enb} = '1' then
+
+@{data_out} <= @{data1_in} and @{data2_in} and @{data3_in};
+@{data_out_enb} <= '1';
+
+end if;
+end if;
+
+end process and_process;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="1"/>
+ <consumption>
+ <input pattern="1" name="data1_in_enb"/>
+ <input pattern="1" name="data2_in_enb"/>
+ <input pattern="1" name="data3_in_enb"/>
+ </consumption>
+ <production counter="1">
+ <output pattern="01" name="data_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
<!DOCTYPE rgb3sx8_to_gs>
-<block_impl ref_md5="" ref_name="rgb3sx8_to_gs.xml">
+<block_impl ref_name="rgb3sx8_to_gs.xml" ref_md5="">
<comments>
- <author mail="" lastname="" firstname=""/>
- <date creation=""/>
- <description>vcdsv</description>
- <notes>vrevgfregaqv</notes>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>fez</description>
+ <notes>fez</notes>
</comments>
<libraries>
<library name="ieee">
cst_mult <= to_unsigned(87382, 18);
-accum_process : process (clk, reset)
+accum_process : process (@{clk}, @{reset})
begin
-if reset = '1' then
+if @{reset} = '1' then
count <= to_unsigned(0, 3);
accum <= to_unsigned(0, dsp_in_width);
do_mult <= '0';
-elsif rising_edge(clk) then
+elsif rising_edge(@{clk}) then
do_mult <= '0';
-if rgb_in_enb = '1' then
+if @{rgb_in_enb} = '1' then
if count = 0 then
-accum <= resize(unsigned(rgb_in), dsp_in_width);
+accum <= resize(unsigned(@{rgb_in}), dsp_in_width);
count <= to_unsigned(1, 3);
elsif count = 1 then
-accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+accum <= accum + resize(unsigned(@{rgb_in}), dsp_in_width);
count <= to_unsigned(2, 3);
elsif count = 2 then
-accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+accum <= accum + resize(unsigned(@{rgb_in}), dsp_in_width);
count <= to_unsigned(0, 3);
do_mult <= '1';
end if;
end process accum_process;
-mult_process : process (clk, reset)
+mult_process : process (@{clk}, @{reset})
begin
-if reset = '1' then
+if @{reset} = '1' then
result <= to_unsigned(0, dsp_out_width);
do_out <= '0';
-elsif rising_edge(clk) then
+elsif rising_edge(@{clk}) then
do_out <= '0';
if do_mult = '1' then
end if;
end process mult_process;
-gs_out <= std_logic_vector(result(dsp_in_width+7 downto dsp_in_width));
-gs_out_enb <= do_out;
+@{gs_out} <= std_logic_vector(result(dsp_in_width+7 downto dsp_in_width));
+@{gs_out_enb} <= do_out;
end rtl;
</architecture>
<patterns>
- <delta value="to_define"/>
+ <delta value="3"/>
<consumption>
- <input name="rgb_in_enb" pattern="to_define"/>
+ <input pattern="111" name="rgb_in_enb"/>
</consumption>
- <production counter="to_define">
- <output name="gs_out_enb" pattern="to_define"/>
+ <production counter="3">
+ <output pattern="00001" name="gs_out_enb"/>
</production>
</patterns>
</block_impl>
--- /dev/null
+<!DOCTYPE rgb3sx8_to_ycbcr_3DSP>
+<block_impl ref_name="rgb3sx8_to_ycbcr_3DSP.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>fez</description>
+ <notes>fez</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+component mult_accum
+port (
+@{clk} : in std_logic;
+ce : in std_logic;
+sclr : in std_logic;
+bypass : in std_logic;
+a : in std_logic_vector(17 downto 0);
+b : in std_logic_vector(17 downto 0);
+s : out std_logic_vector(47 downto 0)
+);
+end component;
+
+-- Signals
+signal do_sum_y : std_logic;
+signal do_sum_y_dly : std_logic;
+signal do_sum_cr : std_logic;
+signal do_sum_cr_dly : std_logic;
+signal do_sum_cb : std_logic;
+signal do_sum_cb_dly : std_logic;
+signal do_out : std_logic;
+signal do_out_cr : std_logic;
+signal do_out_cb : std_logic;
+signal do_out_y : std_logic;
+signal count_y : unsigned (2 downto 0);
+signal count_cr : unsigned (2 downto 0);
+signal count_cb : unsigned (2 downto 0);
+signal y : signed(8 downto 0);
+signal y_dly1 : signed(8 downto 0);
+signal y_dly2 : signed(8 downto 0);
+signal cb : signed(8 downto 0);
+signal cb_dly1 : signed(8 downto 0);
+signal cr : signed(8 downto 0);
+signal cst_y_r : signed(17 downto 0);
+signal cst_y_g : signed(17 downto 0);
+signal cst_y_b : signed(17 downto 0);
+signal cst_cb_r : signed(17 downto 0);
+signal cst_cb_g : signed(17 downto 0);
+signal cst_cb_b : signed(17 downto 0);
+signal cst_cr_r : signed(17 downto 0);
+signal cst_cr_g : signed(17 downto 0);
+signal cst_cr_b : signed(17 downto 0);
+
+signal bypass_y : std_logic;
+signal a_y : std_logic_vector(17 downto 0);
+signal b_y : std_logic_vector(17 downto 0);
+signal s_y : std_logic_vector(47 downto 0);
+signal bypass_cr : std_logic;
+signal a_cr : std_logic_vector(17 downto 0);
+signal b_cr : std_logic_vector(17 downto 0);
+signal s_cr : std_logic_vector(47 downto 0);
+signal bypass_cb : std_logic;
+signal a_cb : std_logic_vector(17 downto 0);
+signal b_cb : std_logic_vector(17 downto 0);
+signal s_cb : std_logic_vector(47 downto 0);
+
+signal compo_out : std_logic_vector(7 downto 0);
+
+begin
+
+y_multiplier : mult_accum
+port map (
+@{clk} => @{clk},
+ce => '1',
+sclr => '0',
+bypass => bypass_y,
+a => a_y,
+b => b_y,
+s => s_y
+);
+cr_multiplier : mult_accum
+port map (
+@{clk} => @{clk},
+ce => '1',
+sclr => '0',
+bypass => bypass_cr,
+a => a_cr,
+b => b_cr,
+s => s_cr
+);
+cb_multiplier : mult_accum
+port map (
+@{clk} => @{clk},
+ce => '1',
+sclr => '0',
+bypass => bypass_cb,
+a => a_cb,
+b => b_cb,
+s => s_cb
+);
+
+
+cst_y_r <= to_signed(33658, 18);
+cst_y_g <= to_signed(66077, 18);
+cst_y_b <= to_signed(12833, 18);
+cst_cb_r <= to_signed(-19428, 18);
+cst_cb_g <= to_signed(-38141, 18);
+cst_cb_b <= to_signed(57569, 18);
+cst_cr_r <= to_signed(57569, 18);
+cst_cr_g <= to_signed(-48207, 18);
+cst_cr_b <= to_signed(-9362, 18);
+
+multy_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+a_y <= (others => '0');
+b_y <= (others => '0');
+
+count_y <= to_unsigned(0, 3);
+do_sum_y <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_sum_y <= '0';
+
+a_y <= (others => '0');
+b_y <= (others => '0');
+
+if @{rgb_in_enb} = '1' then
+
+a_y <= "0000000000" & @{rgb_in};
+
+if count_y = 0 then
+b_y <= std_logic_vector(cst_y_b);
+
+count_y <= to_unsigned(1, 3);
+
+elsif count_y = 1 then
+b_y <= std_logic_vector(cst_y_g);
+count_y <= to_unsigned(2, 3);
+
+elsif count_y = 2 then
+b_y <= std_logic_vector(cst_y_r);
+count_y <= to_unsigned(0, 3);
+do_sum_y <= '1';
+end if;
+end if;
+end if;
+end process multy_process;
+
+sumy_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+bypass_y <= '0';
+y <= to_signed(0, 9);
+y_dly1 <= to_signed(0, 9);
+y_dly2 <= to_signed(0, 9);
+
+elsif rising_edge(@{clk}) then
+bypass_y <= do_sum_y;
+do_sum_y_dly <= do_sum_y;
+y_dly1 <= y;
+y_dly2 <= y_dly1;
+
+if do_sum_y_dly = '1' then
+y <= to_signed(16, 9) + signed(s_y(25 downto 17));
+end if;
+end if;
+
+end process sumy_process;
+
+multcb_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+a_cb <= (others => '0');
+b_cb <= (others => '0');
+
+count_cb <= to_unsigned(0, 3);
+do_sum_cb <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_sum_cb <= '0';
+
+a_cb <= (others => '0');
+b_cb <= (others => '0');
+
+if @{rgb_in_enb} = '1' then
+
+a_cb <= "0000000000" & @{rgb_in};
+
+if count_cb = 0 then
+b_cb <= std_logic_vector(cst_cb_b);
+
+count_cb <= to_unsigned(1, 3);
+
+elsif count_cb = 1 then
+b_cb <= std_logic_vector(cst_cb_g);
+count_cb <= to_unsigned(2, 3);
+
+elsif count_cb = 2 then
+b_cb <= std_logic_vector(cst_cb_r);
+count_cb <= to_unsigned(0, 3);
+do_sum_cb <= '1';
+end if;
+end if;
+end if;
+end process multcb_process;
+
+sumcb_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+bypass_cb <= '0';
+cb <= to_signed(0, 9);
+cb_dly1 <= to_signed(0, 9);
+elsif rising_edge(@{clk}) then
+bypass_cb <= do_sum_cb;
+do_sum_cb_dly <= do_sum_cb;
+cb_dly1 <= cb;
+
+if do_sum_cb_dly = '1' then
+cb <= to_signed(128, 9) + signed(s_cb(25 downto 17));
+end if;
+end if;
+
+end process sumcb_process;
+
+multcr_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+a_cr <= (others => '0');
+b_cr <= (others => '0');
+
+count_cr <= to_unsigned(0, 3);
+do_sum_cr <= '0';
+
+elsif rising_edge(@{clk}) then
+
+do_sum_cr <= '0';
+
+a_cr <= (others => '0');
+b_cr <= (others => '0');
+
+if @{rgb_in_enb} = '1' then
+
+a_cr <= "0000000000" & @{rgb_in};
+
+if count_cr = 0 then
+b_cr <= std_logic_vector(cst_cr_b);
+
+count_cr <= to_unsigned(1, 3);
+
+elsif count_cr = 1 then
+b_cr <= std_logic_vector(cst_cr_g);
+count_cr <= to_unsigned(2, 3);
+
+elsif count_cr = 2 then
+b_cr <= std_logic_vector(cst_cr_r);
+count_cr <= to_unsigned(0, 3);
+do_sum_cr <= '1';
+end if;
+end if;
+end if;
+end process multcr_process;
+
+sumcr_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+bypass_cr <= '0';
+cr <= to_signed(0, 9);
+do_out_cr <= '0';
+
+elsif rising_edge(@{clk}) then
+bypass_cr <= do_sum_cr;
+do_sum_cr_dly <= do_sum_cr;
+do_out_cr <= '0';
+
+if do_sum_cr_dly = '1' then
+do_out_cr <= '1';
+cr <= to_signed(128, 9) + signed(s_cr(25 downto 17));
+end if;
+end if;
+end process sumcr_process;
+
+out_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+do_out_y <= '0';
+do_out_cb <= '0';
+elsif rising_edge(@{clk}) then
+do_out_cb <= do_out_cr;
+do_out_y <= do_out_cb;
+end if;
+end process out_process;
+
+
+@{ycbcr_out} <= std_logic_vector(y_dly2(7 downto 0)) when do_out_y = '1' else
+std_logic_vector(cb_dly1(7 downto 0)) when do_out_cb = '1' else
+std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
+(others => '0');
+@{ycbcr_out_enb} <= do_out_y or do_out_cb or do_out_cr;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="3"/>
+ <consumption>
+ <input pattern="111" name="rgb_in_enb"/>
+ </consumption>
+ <production counter="3,3,3">
+ <output pattern="00000111" name="ycbcr_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<!DOCTYPE threshold_extctl>
+<block_impl ref_name="threshold_extctl.xml" ref_md5="">
+ <comments>
+ <author lastname="" mail="" firstname=""/>
+ <date creation="2018-01-10"/>
+ <related_files list=""/>
+ <description>fez</description>
+ <notes>fez</notes>
+ </comments>
+ <libraries>
+ <library name="ieee">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+ <architecture>
+-- Signals
+signal def_val : unsigned(in_width-1 downto 0);
+
+begin
+
+def_val <= to_unsigned(default_value, in_width);
+
+threshold_process : process (@{clk}, @{reset})
+begin
+if @{reset} = '1' then
+
+@{data_out_enb} <= '0';
+@{data_out} <= (others => '0');
+
+elsif rising_edge(@{clk}) then
+
+@{data_out_enb} <= '0';
+
+if @{data_in_enb} = '1' and @{keep_in_enb} = '1' then
+
+if @{keep_in} = '1' then
+@{data_out} <= @{data_in};
+else
+@{data_out} <= std_logic_vector(def_val);
+end if;
+@{data_out_enb} <= '1';
+end if;
+end if;
+end process threshold_process;
+
+end rtl;
+</architecture>
+ <patterns>
+ <delta value="1"/>
+ <consumption>
+ <input pattern="1" name="data_in_enb"/>
+ <input pattern="1" name="keep_in_enb"/>
+ </consumption>
+ <production counter="1">
+ <output pattern="01" name="data_out_enb"/>
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<!DOCTYPE boxfilter_3x3>
+<block version="0.1">
+ <informations>
+ <name>boxfilter_3x3</name>
+ <category ids=""/>
+ <description>
+ <brief>frdfgdr</brief>
+ <detailed>gregre</detailed>
+ </description>
+ </informations>
+ <parameters>
+ <parameter value="128" type="natural" context="generic" name="img_width"/>
+ <parameter value="128" type="natural" context="generic" name="img_height"/>
+ <parameter value="18" type="natural" context="generic" name="dsp_in_width"/>
+ <parameter value="36" type="natural" context="generic" name="dsp_out_width"/>
+ </parameters>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="pix_in"/>
+ <control iface="pix_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="pix_out"/>
+ <control iface="pix_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<!DOCTYPE checker>
+<block version="0.1">
+ <informations>
+ <name>checker</name>
+ <category ids=""/>
+ <description>
+ <brief>gre</brief>
+ <detailed>gre</detailed>
+ </description>
+ </informations>
+ <parameters>
+ <parameter value="8" type="natural" context="generic" name="in_width"/>
+ <parameter value="1" type="natural" context="generic" name="check_type"/>
+ <parameter value="0" type="natural" context="generic" name="inf_value"/>
+ <parameter value="0" type="natural" context="generic" name="sup_value"/>
+ </parameters>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data_in"/>
+ <control iface="data_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data_out"/>
+ <output endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="check_out"/>
+ <control iface="data_out"/>
+ <control iface="check_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<block>
+ <informations>
+ <name>
+ generator-csvreader
+ </name>
+ <category ids="6" />
+ <description>
+ <brief>
+ generates data from a csv file
+ </brief>
+ <detailed>
+ generates data from a csv file
+ </detailed>
+ </description>
+ </informations>
+
+ <parameters>
+
+ <parameter name="row_length" type="positive" value="24" context="generic"/>
+ <parameter name="nb_row" type="positive" value="8" context="generic"/>
+ <parameter name="data_width" type="positive" value="8" context="generic"/>
+ <parameter name="img_file" type="string" value="nofile.csv" context="user"/>
+ <parameter name="out_pattern_sub" type="expression" value="row" context="user"/>
+ <parameter name="out_pattern" type="expression" value="(10){$row_length*$nb_$out_pattern_sub}" context="user"/>
+ </parameters>
+
+ <interfaces>
+ <inputs>
+ <input name="clk" width="1" purpose="clock" />
+ <input name="rst" width="1" purpose="reset" />
+ </inputs>
+ <outputs>
+ <output name="data_out" width="$data_width"/>
+ <control iface="data_out"/>
+ </outputs>
+ </interfaces>
+
+</block>
--- /dev/null
+<!DOCTYPE deserializer_3x1>
+<block version="0.1">
+ <informations>
+ <name>deserializer_3x1</name>
+ <category ids=""/>
+ <description>
+ <brief>gre</brief>
+ <detailed>gre</detailed>
+ </description>
+ </informations>
+ <parameters>
+ <parameter value="8" type="natural" context="generic" name="in_width"/>
+ </parameters>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data_in"/>
+ <control iface="data_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data1_out"/>
+ <output endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data2_out"/>
+ <output endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data3_out"/>
+ <control iface="data1_out"/>
+ <control iface="data2_out"/>
+ <control iface="data3_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<!DOCTYPE logical_AND_3>
+<block version="0.1">
+ <informations>
+ <name>logical_AND_3</name>
+ <category ids=""/>
+ <description>
+ <brief>yt</brief>
+ <detailed>hyjt</detailed>
+ </description>
+ </informations>
+ <parameters/>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="data1_in"/>
+ <input endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="data2_in"/>
+ <input endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="data3_in"/>
+ <control iface="data1_in"/>
+ <control iface="data2_in"/>
+ <control iface="data3_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="data_out"/>
+ <control iface="data_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<!DOCTYPE rgb3sx8_to_gs>
+<block version="0.1">
+ <informations>
+ <name>rgb3sx8_to_gs</name>
+ <category ids=""/>
+ <description>
+ <brief>fez</brief>
+ <detailed>fez</detailed>
+ </description>
+ </informations>
+ <parameters>
+ <parameter value="18" type="natural" context="generic" name="dsp_in_width"/>
+ <parameter value="36" type="natural" context="generic" name="dsp_out_width"/>
+ </parameters>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="rgb_in"/>
+ <control iface="rgb_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="gs_out"/>
+ <control iface="gs_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<!DOCTYPE rgb3sx8_to_ycbcr_3DSP>
+<block version="0.1">
+ <informations>
+ <name>rgb3sx8_to_ycbcr_3DSP</name>
+ <category ids=""/>
+ <description>
+ <brief>fez</brief>
+ <detailed>fez</detailed>
+ </description>
+ </informations>
+ <parameters/>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="rgb_in"/>
+ <control iface="rgb_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="natural" purpose="data" multiplicity="1" width="7" name="ycbcr_out"/>
+ <control iface="ycbcr_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+<!DOCTYPE threshold_extctl>
+<block version="0.1">
+ <informations>
+ <name>threshold_extctl</name>
+ <category ids=""/>
+ <description>
+ <brief>fez</brief>
+ <detailed>fez</detailed>
+ </description>
+ </informations>
+ <parameters>
+ <parameter value="8" type="natural" context="generic" name="in_width"/>
+ <parameter value="0" type="natural" context="generic" name="default_value"/>
+ </parameters>
+ <interfaces>
+ <inputs>
+ <input endian="little" type="boolean" purpose="clock" multiplicity="1" width="1" name="clk"/>
+ <input endian="little" type="boolean" purpose="reset" multiplicity="1" width="1" name="reset"/>
+ <input endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data_in"/>
+ <input endian="little" type="boolean" purpose="data" multiplicity="1" width="1" name="keep_in"/>
+ <control iface="data_in"/>
+ <control iface="keep_in"/>
+ </inputs>
+ <outputs>
+ <output endian="little" type="expression" purpose="data" multiplicity="1" width="$in_width" name="data_out"/>
+ <control iface="data_out"/>
+ </outputs>
+ </interfaces>
+</block>
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : logical_AND_3.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a logical AND on three inputs.
+--
+--
+-- Note :
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity logical_AND_3 is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic;
+ data1_in_enb : in std_logic;
+ data2_in : in std_logic;
+ data2_in_enb : in std_logic;
+ data3_in : in std_logic;
+ data3_in_enb : in std_logic;
+
+ data_out : out std_logic;
+ data_out_enb : out std_logic -- the control signal, common to all output
+ );
+end logical_AND_3;
+
+
+architecture rtl of logical_AND_3 is
+
+begin
+
+ and_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ data_out <= '0';
+ data_out_enb <= '0';
+
+ elsif rising_edge(clk) then
+
+ data_out <= '0';
+ data_out_enb <= '0';
+
+ if data1_in_enb = '1' and data2_in_enb = '1' and data3_in_enb = '1' then
+
+ data_out <= data1_in and data2_in and data3_in;
+ data_out_enb <= '1';
+
+ end if;
+ end if;
+
+ end process and_process;
+
+end rtl;
+
$(BUILDPATH)/FunctionalInterface.o \
$(BUILDPATH)/GroupInterface.o \
$(BUILDPATH)/ReferenceInterface.o \
+ $(BUILDPATH)/AbstractInputModifier.o \
+ $(BUILDPATH)/DelayInputModifier.o \
$(BUILDPATH)/BlockImplementation.o \
$(BUILDPATH)/Graph.o \
$(BUILDPATH)/AbstractBoxItem.o \
<xs:attribute ref="to" />
</xs:attributeGroup>
+ <xs:attributeGroup name="modifierAttrGroup">
+ <xs:attribute ref="id" />
+ <xs:attribute ref="type" />
+ <xs:attribute ref="params" />
+ </xs:attributeGroup>
+
<!-- déclaration des attributs -->
<xs:attribute name="ref_md5" type="xs:string"/>
<xs:attribute name="context" type="xs:string"/>
<xs:attribute name="type" type="xs:string"/>
+ <xs:attribute name="params" type="xs:string"/>
<!-- déclaration des groupes d'éléments -->
<xs:group name="rootElmtGroup">
<xs:sequence>
<xs:element ref="scenes"/>
- <xs:element ref="connections"/>
+ <xs:element ref="connections"/>
+ <xs:element ref="modifiers"/>
</xs:sequence>
</xs:group>
</xs:complexType>
</xs:element>
+ <xs:element name="modifiers">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element ref="modifier" minOccurs="0" maxOccurs="unbounded"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+
+ <xs:element name="modifier">
+ <xs:complexType>
+ <xs:attributeGroup ref="modifierAttrGroup"/>
+ </xs:complexType>
+ </xs:element>
+
<!-- racine du document -->
<xs:element name="blast_project">
<xs:attribute name="type" type="typeiface"/>
<xs:attribute ref="purpose"/>
<xs:attribute ref="multiplicity"/>
+ <xs:attribute name="endian" type="typeendian" use="optional"/>
</xs:attributeGroup>
<xs:enumeration value="natural"/>
</xs:restriction>
</xs:simpleType>
+
+ <xs:simpleType name="typeendian">
+ <xs:restriction base="xs:string">
+ <xs:enumeration value="little"/>
+ <xs:enumeration value="big"/>
+ </xs:restriction>
+ </xs:simpleType>
<xs:attribute name="wishbone" type="xs:string"/>
<xs:attribute name="context" type="xs:string" />
<!-- Racine du document -->
<xs:element name="block">
- <xs:complexType>
- <xs:group ref="blockElmtGroup"/>
- </xs:complexType>
+ <xs:complexType>
+ <xs:group ref="blockElmtGroup"/>
+ <xs:attribute name="version" type="xs:string" use="optional" />
+ </xs:complexType>
</xs:element>
</xs:schema>
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : rgb3sx8_to_gs.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a conversion from rgb24 (8 bits/serial) to grayscale
+--
+-- Note : rgb24 (8 bits/serial) pixels are composed of three 8 bits
+-- values that are consumed on port rgb_in, in the following
+-- order : blue, green, red.
+-- output value on gs_out is computed with (red+green+blue)/3
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rgb3sx8_to_gs is
+ generic(
+ dsp_in_width : natural := 18;
+ dsp_out_width : natural := 36
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ rgb_in : in std_logic_vector(7 downto 0);
+ rgb_in_enb : in std_logic;
+ gs_out : out std_logic_vector(7 downto 0);
+ gs_out_enb : out std_logic
+
+ );
+end rgb3sx8_to_gs;
+
+
+architecture rtl of rgb3sx8_to_gs is
+
+ -- Signals
+ signal do_mult : std_logic;
+ signal do_out : std_logic;
+ signal count : unsigned (2 downto 0);
+ signal accum : unsigned(dsp_in_width-1 downto 0);
+ signal result : unsigned(dsp_out_width-1 downto 0);
+ signal cst_mult : unsigned(dsp_in_width-1 downto 0); -- eq. 87382 to do /3
+
+begin
+
+ cst_mult <= to_unsigned(87382, 18);
+
+ accum_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ count <= to_unsigned(0, 3);
+ accum <= to_unsigned(0, dsp_in_width);
+ do_mult <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_mult <= '0';
+
+ if rgb_in_enb = '1' then
+
+ if count = 0 then
+ accum <= resize(unsigned(rgb_in), dsp_in_width);
+ count <= to_unsigned(1, 3);
+ elsif count = 1 then
+ accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+ count <= to_unsigned(2, 3);
+ elsif count = 2 then
+ accum <= accum + resize(unsigned(rgb_in), dsp_in_width);
+ count <= to_unsigned(0, 3);
+ do_mult <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process accum_process;
+
+ mult_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ result <= to_unsigned(0, dsp_out_width);
+ do_out <= '0';
+ elsif rising_edge(clk) then
+
+ do_out <= '0';
+ if do_mult = '1' then
+ result <= accum * cst_mult;
+ do_out <= '1';
+ end if;
+ end if;
+ end process mult_process;
+
+ gs_out <= std_logic_vector(result(dsp_in_width+7 downto dsp_in_width));
+ gs_out_enb <= do_out;
+
+end rtl;
+
+++ /dev/null
-<!DOCTYPE rgb3sx8_to_gs>
-<block version="0.1">
- <informations>
- <name>rgb3sx8_to_gs</name>
- <category ids=""/>
- <description>
- <brief>vcdsv</brief>
- <detailed>vrevgfregaqv</detailed>
- </description>
- </informations>
- <parameters>
- <parameter name="dsp_in_width" context="generic" value="18" type="natural"/>
- <parameter name="dsp_out_width" context="generic" value="36" type="natural"/>
- </parameters>
- <interfaces>
- <inputs>
- <input name="clk" width="1" endian="little" purpose="clock" type="boolean" multiplicity="1"/>
- <input name="reset" width="1" endian="little" purpose="reset" type="boolean" multiplicity="1"/>
- <input name="rgb_in" width="7" endian="little" purpose="data" type="natural" multiplicity="1"/>
- <control iface="rgb_in"/>
- </inputs>
- <outputs>
- <output name="gs_out" width="7" endian="little" purpose="data" type="natural" multiplicity="1"/>
- <control iface="gs_out"/>
- </outputs>
- </interfaces>
-</block>
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : rgb3sx8_to_ycbcr_3DSP.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a conversion from rgb24 (8 bits/serial) to YCrCb
+--
+-- Note : rgb24 (8 bits/serial) pixels are composed of three 8 bits
+-- values that are consumed on port rgb_in, in the following
+-- order : blue, green, red.
+-- output values on ycrcb_out are produced in the following
+-- order: cb, cr, y
+-- They are computed using ITU-R BT.601 conversion principles,
+-- assuming that RGB component are digital and thus rangin
+-- from 0 to 255. Formulas are:
+-- Y = 16 + 65.738R/256 + 129.057G/256 + 25.064B/256
+-- Cb = 128 - 37.945R/256 - 74.494G/256 + 112.439B/256
+-- Cr = 128 + 112.439R/256 - 94.154G/256 - 18.285B/256
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rgb3sx8_to_ycbcr_3DSP is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ rgb_in : in std_logic_vector(7 downto 0);
+ rgb_in_enb : in std_logic;
+ ycbcr_out : out std_logic_vector(7 downto 0);
+ ycbcr_out_enb : out std_logic
+
+ );
+end rgb3sx8_to_ycbcr_3DSP;
+
+
+architecture rtl of rgb3sx8_to_ycbcr_3DSP is
+
+ component mult_accum
+ port (
+ clk : in std_logic;
+ ce : in std_logic;
+ sclr : in std_logic;
+ bypass : in std_logic;
+ a : in std_logic_vector(17 downto 0);
+ b : in std_logic_vector(17 downto 0);
+ s : out std_logic_vector(47 downto 0)
+ );
+ end component;
+
+-- Signals
+ signal do_sum_y : std_logic;
+ signal do_sum_y_dly : std_logic;
+ signal do_sum_cr : std_logic;
+ signal do_sum_cr_dly : std_logic;
+ signal do_sum_cb : std_logic;
+ signal do_sum_cb_dly : std_logic;
+ signal do_out : std_logic;
+ signal do_out_cr : std_logic;
+ signal do_out_cb : std_logic;
+ signal do_out_y : std_logic;
+ signal count_y : unsigned (2 downto 0);
+ signal count_cr : unsigned (2 downto 0);
+ signal count_cb : unsigned (2 downto 0);
+ signal y : signed(8 downto 0);
+ signal y_dly1 : signed(8 downto 0);
+ signal y_dly2 : signed(8 downto 0);
+ signal cb : signed(8 downto 0);
+ signal cb_dly1 : signed(8 downto 0);
+ signal cr : signed(8 downto 0);
+ signal cst_y_r : signed(17 downto 0);
+ signal cst_y_g : signed(17 downto 0);
+ signal cst_y_b : signed(17 downto 0);
+ signal cst_cb_r : signed(17 downto 0);
+ signal cst_cb_g : signed(17 downto 0);
+ signal cst_cb_b : signed(17 downto 0);
+ signal cst_cr_r : signed(17 downto 0);
+ signal cst_cr_g : signed(17 downto 0);
+ signal cst_cr_b : signed(17 downto 0);
+
+ signal bypass_y : std_logic;
+ signal a_y : std_logic_vector(17 downto 0);
+ signal b_y : std_logic_vector(17 downto 0);
+ signal s_y : std_logic_vector(47 downto 0);
+ signal bypass_cr : std_logic;
+ signal a_cr : std_logic_vector(17 downto 0);
+ signal b_cr : std_logic_vector(17 downto 0);
+ signal s_cr : std_logic_vector(47 downto 0);
+ signal bypass_cb : std_logic;
+ signal a_cb : std_logic_vector(17 downto 0);
+ signal b_cb : std_logic_vector(17 downto 0);
+ signal s_cb : std_logic_vector(47 downto 0);
+
+ signal compo_out : std_logic_vector(7 downto 0);
+
+begin
+
+ y_multiplier : mult_accum
+ port map (
+ clk => clk,
+ ce => '1',
+ sclr => '0',
+ bypass => bypass_y,
+ a => a_y,
+ b => b_y,
+ s => s_y
+ );
+ cr_multiplier : mult_accum
+ port map (
+ clk => clk,
+ ce => '1',
+ sclr => '0',
+ bypass => bypass_cr,
+ a => a_cr,
+ b => b_cr,
+ s => s_cr
+ );
+ cb_multiplier : mult_accum
+ port map (
+ clk => clk,
+ ce => '1',
+ sclr => '0',
+ bypass => bypass_cb,
+ a => a_cb,
+ b => b_cb,
+ s => s_cb
+ );
+
+
+ cst_y_r <= to_signed(33658, 18);
+ cst_y_g <= to_signed(66077, 18);
+ cst_y_b <= to_signed(12833, 18);
+ cst_cb_r <= to_signed(-19428, 18);
+ cst_cb_g <= to_signed(-38141, 18);
+ cst_cb_b <= to_signed(57569, 18);
+ cst_cr_r <= to_signed(57569, 18);
+ cst_cr_g <= to_signed(-48207, 18);
+ cst_cr_b <= to_signed(-9362, 18);
+
+ multy_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ a_y <= (others => '0');
+ b_y <= (others => '0');
+
+ count_y <= to_unsigned(0, 3);
+ do_sum_y <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_sum_y <= '0';
+
+ a_y <= (others => '0');
+ b_y <= (others => '0');
+
+ if rgb_in_enb = '1' then
+
+ a_y <= "0000000000" & rgb_in;
+
+ if count_y = 0 then
+ b_y <= std_logic_vector(cst_y_b);
+
+ count_y <= to_unsigned(1, 3);
+
+ elsif count_y = 1 then
+ b_y <= std_logic_vector(cst_y_g);
+ count_y <= to_unsigned(2, 3);
+
+ elsif count_y = 2 then
+ b_y <= std_logic_vector(cst_y_r);
+ count_y <= to_unsigned(0, 3);
+ do_sum_y <= '1';
+ end if;
+ end if;
+ end if;
+ end process multy_process;
+
+ sumy_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ bypass_y <= '0';
+ y <= to_signed(0, 9);
+ y_dly1 <= to_signed(0, 9);
+ y_dly2 <= to_signed(0, 9);
+
+ elsif rising_edge(clk) then
+ bypass_y <= do_sum_y;
+ do_sum_y_dly <= do_sum_y;
+ y_dly1 <= y;
+ y_dly2 <= y_dly1;
+
+ if do_sum_y_dly = '1' then
+ y <= to_signed(16, 9) + signed(s_y(25 downto 17));
+ end if;
+ end if;
+
+ end process sumy_process;
+
+ multcb_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ a_cb <= (others => '0');
+ b_cb <= (others => '0');
+
+ count_cb <= to_unsigned(0, 3);
+ do_sum_cb <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_sum_cb <= '0';
+
+ a_cb <= (others => '0');
+ b_cb <= (others => '0');
+
+ if rgb_in_enb = '1' then
+
+ a_cb <= "0000000000" & rgb_in;
+
+ if count_cb = 0 then
+ b_cb <= std_logic_vector(cst_cb_b);
+
+ count_cb <= to_unsigned(1, 3);
+
+ elsif count_cb = 1 then
+ b_cb <= std_logic_vector(cst_cb_g);
+ count_cb <= to_unsigned(2, 3);
+
+ elsif count_cb = 2 then
+ b_cb <= std_logic_vector(cst_cb_r);
+ count_cb <= to_unsigned(0, 3);
+ do_sum_cb <= '1';
+ end if;
+ end if;
+ end if;
+ end process multcb_process;
+
+ sumcb_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ bypass_cb <= '0';
+ cb <= to_signed(0, 9);
+ cb_dly1 <= to_signed(0, 9);
+ elsif rising_edge(clk) then
+ bypass_cb <= do_sum_cb;
+ do_sum_cb_dly <= do_sum_cb;
+ cb_dly1 <= cb;
+
+ if do_sum_cb_dly = '1' then
+ cb <= to_signed(128, 9) + signed(s_cb(25 downto 17));
+ end if;
+ end if;
+
+ end process sumcb_process;
+
+ multcr_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ a_cr <= (others => '0');
+ b_cr <= (others => '0');
+
+ count_cr <= to_unsigned(0, 3);
+ do_sum_cr <= '0';
+
+ elsif rising_edge(clk) then
+
+ do_sum_cr <= '0';
+
+ a_cr <= (others => '0');
+ b_cr <= (others => '0');
+
+ if rgb_in_enb = '1' then
+
+ a_cr <= "0000000000" & rgb_in;
+
+ if count_cr = 0 then
+ b_cr <= std_logic_vector(cst_cr_b);
+
+ count_cr <= to_unsigned(1, 3);
+
+ elsif count_cr = 1 then
+ b_cr <= std_logic_vector(cst_cr_g);
+ count_cr <= to_unsigned(2, 3);
+
+ elsif count_cr = 2 then
+ b_cr <= std_logic_vector(cst_cr_r);
+ count_cr <= to_unsigned(0, 3);
+ do_sum_cr <= '1';
+ end if;
+ end if;
+ end if;
+ end process multcr_process;
+
+ sumcr_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ bypass_cr <= '0';
+ cr <= to_signed(0, 9);
+ do_out_cr <= '0';
+
+ elsif rising_edge(clk) then
+ bypass_cr <= do_sum_cr;
+ do_sum_cr_dly <= do_sum_cr;
+ do_out_cr <= '0';
+
+ if do_sum_cr_dly = '1' then
+ do_out_cr <= '1';
+ cr <= to_signed(128, 9) + signed(s_cr(25 downto 17));
+ end if;
+ end if;
+ end process sumcr_process;
+
+ out_process : process (clk, reset)
+ begin
+ if reset = '1' then
+ do_out_y <= '0';
+ do_out_cb <= '0';
+ elsif rising_edge(clk) then
+ do_out_cb <= do_out_cr;
+ do_out_y <= do_out_cb;
+ end if;
+ end process out_process;
+
+
+ ycbcr_out <= std_logic_vector(y_dly2(7 downto 0)) when do_out_y = '1' else
+ std_logic_vector(cb_dly1(7 downto 0)) when do_out_cb = '1' else
+ std_logic_vector(cr(7 downto 0)) when do_out_cr = '1' else
+ (others => '0');
+ ycbcr_out_enb <= do_out_y or do_out_cb or do_out_cr;
+
+end rtl;
+
--- /dev/null
+-------------------------------------------------------------------------------
+--
+-- File : threshold _extctl.vhd
+-- Related files :
+--
+-- Author(s) : stephane Domas (sdomas@univ-fcomte.fr)
+--
+-- Creation Date : 2017/10/16
+--
+-- Description : This IP does a threshold based on a external signal
+--
+--
+-- Note : input data is kept as is depending on the fact that
+-- the keep_in signal is asserted to 1 or not. It it is not,
+-- then input is replaced by the default_value given as a
+-- generic. Note that keep_in_enb and data_in_enb must be
+-- asserted to 1 at the same time so that the block gives an output
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity threshold_extctl is
+ generic(
+ in_width : natural := 8;
+ default_value : natural := 0
+ );
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(in_width-1 downto 0);
+ data_in_enb : in std_logic;
+ keep_in : in std_logic;
+ keep_in_enb : in std_logic;
+ data_out : out std_logic_vector(in_width-1 downto 0);
+ data_out_enb : out std_logic
+
+ );
+end threshold_extctl;
+
+
+architecture rtl of threshold_extctl is
+
+ -- Signals
+ signal def_val : unsigned(in_width-1 downto 0);
+
+begin
+
+ def_val <= to_unsigned(default_value, in_width);
+
+ threshold_process : process (clk, reset)
+ begin
+ if reset = '1' then
+
+ data_out_enb <= '0';
+ data_out <= (others => '0');
+
+ elsif rising_edge(clk) then
+
+ data_out_enb <= '0';
+
+ if data_in_enb = '1' and keep_in_enb = '1' then
+
+ if keep_in = '1' then
+ data_out <= data_in;
+ else
+ data_out <= std_logic_vector(def_val);
+ end if;
+ data_out_enb <= '1';
+ end if;
+ end if;
+ end process threshold_process;
+
+end rtl;
+
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<blast_project>
- <scenes count="1">
- <scene id="0" upper_scene="-1">
- <group_item id="1" upper_item="-1" name="top group" position="0,38" dimension="343,128">
- <group_ifaces count="0"/>
- </group_item>
- <source_items count="0"/>
- <block_items functional_count="1" group_count="0">
- <bi_functional id="2" ref_xml="/home/sdomas/Projet/Blast/code/blast/lib/references/demux.xml" ref_md5="aeb14abd65f72dbd4af47b7a660cd94e" name="block demultiplexer" position="45,30" dimension="253,68">
- <bif_parameters>
- <bif_parameter name="val_width" value="0"/>
- <bif_parameter name="sel_width" value="$if_nb"/>
- </bif_parameters>
- <bif_ifaces count="5">
- <bif_iface id="1" name="clk" ref_name="clk" orientation="west" position="0"/>
- <bif_iface id="2" name="rst" ref_name="rst" orientation="west" position="0"/>
- <bif_iface id="3" name="val_i" ref_name="val_i" orientation="west" position="0.333333"/>
- <bif_iface id="4" name="sel_i" ref_name="sel_i" orientation="west" position="0.666667"/>
- <bif_iface id="5" name="val_o" ref_name="val_o" orientation="east" position="0.5"/>
- </bif_ifaces>
- </bi_functional>
- </block_items>
- </scene>
- </scenes>
- <connections/>
-</blast_project>
