1 \chapterauthor{Raphaël Couturier}{Femto-ST Institute, University of Franche-Comte, France}
4 \chapter{Presentation of the GPU architecture and of the CUDA environment}
7 \section{Introduction}\label{ch1:intro}
9 This chapter introduces the Graphics Processing Unit (GPU) architecture and all
10 the concepts needed to understand how GPUs work and can be used to speed up the
11 execution of some algorithms. First of all this chapter gives a brief history of
12 the development of the graphics cards up to the point when they started being used in order to make
13 general purpose computation. Then the architecture of a GPU is
14 illustrated. There are many fundamental differences between a GPU and a
15 tradition processor. In order to benefit from the power of a GPU, a CUDA
16 programmer needs to use threads. They have some particularities which enable the
17 CUDA model to be efficient and scalable when some constraints are addressed.
21 \section{Brief history of the video card}
23 Video cards or graphics cards have been introduced in personal computers to
24 produce high quality graphics faster than classical Central Processing Units
25 (CPU) and to free the CPU from this task. In general, display tasks are very
26 repetitive and very specific. Hence, some manufacturers have produced more and
27 more sophisticated video cards, providing 2D accelerations, then 3D accelerations,
28 then some light transforms. Video cards own their own memory to perform their
29 computation. For at least two decades, every personal computer has had a video
30 card which is simple for desktop computers or which provides many accelerations
31 for game and/or graphic-oriented computers. In the latter case, graphic cards
32 may be more expensive than a CPU.
34 Since 2000, video cards have allowed users to apply arithmetic operations
35 simultaneously on a sequence of pixels, later called stream processing. In
36 this case, the information of the pixels (color, location and other information) is
37 combined in order to produce a pixel color that can be displayed on a screen.
38 Simultaneous computations are provided by shaders which calculate rendering
39 effects on graphics hardware with a high degree of flexibility. These shaders
40 handle the stream data with pipelines.
43 Some researchers tried to apply those operations on other data, representing
44 something different from pixels, and consequently this resulted in the first
45 uses of video cards for performing general purpose computation. The programming
46 model was not easy to use at all and was very dependent on the hardware
47 constraints. More precisely it consisted in using either DirectX of OpenGL
48 functions providing an interface to some classical operations for videos
49 operations (memory transfers, texture manipulation, etc.). Floating point
50 operations were most of the time unimaginable. Obviously when something went
51 wrong, programmers had no way (and no tools) to detect it.
55 In order to benefit from the computing power of more recent video cards, CUDA
56 was first proposed in 2007 by NVIDIA. It unifies the programming model for some
57 of their most efficient video cards. CUDA~\cite{ch1:cuda} has quickly been
58 considered by the scientific community as a great advance for general purpose
59 graphics processing unit (GPGPU) computing. Of course other programming models
60 have been proposed. The other well-known alternative is OpenCL which aims at
61 proposing an alternative to CUDA and which is multiplatform and portable. This
62 is a great advantage since it is even possible to execute OpenCL programs on
63 traditional CPUs. The main drawback is that it is less tight with the hardware
64 and consequently sometimes provides less efficient programs. Moreover, CUDA
65 benefits from more mature compilation and optimization procedures. Other less
66 known environments have been proposed, but most of them have been discontinued, for
67 example we can cite, FireStream by ATI which is not maintained anymore and
68 has been replaced by OpenCL, BrookGPU by Standford University~\cite{ch1:Buck:2004:BGS}.
69 Another environment based on pragma (insertion of pragma directives inside the
70 code to help the compiler to generate efficient code) is called OpenACC. For a
71 comparison with OpenCL, interested readers may refer to~\cite{ch1:Dongarra}.
75 \section{Architecture of current GPUs}
77 The architecture \index{architecture of a GPU} of current GPUs is constantly
78 evolving. Nevertheless some trends remain constant throughout this evolution.
79 Processing units composing a GPU are far simpler than a traditional CPU and
80 it is much easier to integrate many computing units inside a GPU card than to do
81 so with many cores inside a CPU. In 2012, the most powerful GPUs contained more than 500
82 cores and the most powerful CPUs had 8
83 cores. Figure~\ref{ch1:fig:comparison_cpu_gpu} shows the number of cores inside
84 a CPU and inside a GPU. In fact, in a current NVIDIA GPU, there are
85 multiprocessors which have 32 cores (for example, on Fermi cards). The core clock
86 of a CPU is generally around 3GHz and the one of a GPU is about 1.5GHz. Although
87 the core clock of GPU cores is slower, the number of cores inside a GPU provides
88 more computational power. This measure is commonly represented by the number of
89 floating point operation per seconds. Nowadays the most powerful GPUs provide more
90 than 1TFlops, i.e., $10^{12}$ floating point operations per second.
91 Nevertheless GPUs are very efficient at executing repetitive work in which
92 only the data change. It is important to keep in mind that multiprocessors
93 inside a GPU have 32 cores. Later we will see that these 32 cores need to do the
94 same work to get maximum performance.
97 \centerline{\includegraphics[]{Chapters/chapter1/figures/nb_cores_CPU_GPU.pdf}}
98 \caption{Comparison of number of cores in a CPU and in a GPU.}
99 %[Comparison of number of cores in a CPU and in a GPU]
100 \label{ch1:fig:comparison_cpu_gpu}
103 On the most powerful GPU cards, called Fermi, multiprocessors are called streaming
104 multiprocessors (SMs). Each SM contains 32 cores and is able to perform 32
105 floating points or integer operations per clock on 32 bit numbers or 16 floating
106 points per clock on 64 bit numbers. SMs have their own registers, execution
107 pipelines and caches. On Fermi architecture, there are 64Kb shared memory plus L1
108 cache and 32,536 32 bit registers per SM. More precisely the programmer can
109 decide what amounts of shared memory and L1 cache SM are to be used. The constraint is
110 that the sum of both amounts should be less than or equal to 64Kb.
112 Threads are used to benefit from the large number of cores of a GPU. These
113 threads are different from traditional threads for a CPU. In
114 Chapter~\ref{chapter2}, some examples of GPU programming will explain the
115 details of the GPU threads. Threads are gathered into blocks of 32
116 threads, called warps. These warps are important when designing an algorithm
120 Another big difference between a CPU and a GPU is the latency of memory. In a CPU,
121 everything is optimized to obtain a low latency architecture. This is possible
122 through the use of cache memories. Moreover, nowadays CPUs carry out many
123 performance optimizations such as speculative execution which roughly speaking
124 consists of executing a small part of the code in advance even if later this work
125 reveals itself to be useless. GPUs do not have low latency
126 memory. In comparison GPUs have small cache memories. Nevertheless the
127 architecture of GPUs is optimized for throughput computation and it takes into
128 account the memory latency.
133 \centerline{\includegraphics[scale=0.7]{Chapters/chapter1/figures/low_latency_vs_high_throughput.pdf}}
134 \caption{Comparison of low latency of a CPU and high throughput of a GPU.}
135 \label{ch1:fig:latency_throughput}
138 Figure~\ref{ch1:fig:latency_throughput} illustrates the main difference of
139 memory latency between a CPU and a GPU. In a CPU, tasks ``ti'' are executed one
140 by one with a short memory latency to get the data to process. After some tasks,
141 there is a context switch that allows the CPU to run concurrent applications
142 and/or multi-threaded applications. {\bf REPHRASE} Memory latencies are longer in a GPU, the
143 principle to obtain a high throughput is to have many tasks to
144 compute. Later we will see that these tasks are called threads with CUDA. With
145 this principle, as soon as a task is finished the next one is ready to be
146 executed while the wait for data for the previous task is overlapped by
147 computation of other tasks. {\bf HERE}
151 \section{Kinds of parallelism}
153 Many kinds of parallelism are available according to the type of hardware.
154 Roughly speaking, there are three classes of parallelism: instruction-level
155 parallelism, data parallelism, and task parallelism.
157 Instruction-level parallelism consists in reordering some instructions in order
158 to execute some of them in parallel without changing the result of the code.
159 In modern CPUs, instruction pipelines allow the processor to execute instructions
160 faster. With a pipeline a processor can execute multiple instructions
161 simultaneously because the output of a task is the input of the
164 Data parallelism consists in executing the same program with different data on
165 different computing units. Of course, no dependency should exist among the
166 data. For example, it is easy to parallelize loops without dependency using the
167 data parallelism paradigm. This paradigm is linked with the Single Instructions
168 Multiple Data (SIMD) architecture. This is the kind of parallelism provided by
171 Task parallelism is the common parallelism achieved on clusters and grids and
172 high performance architectures where different tasks are executed by different
175 \section{CUDA multithreading}
177 The data parallelism of CUDA is more precisely based on the Single Instruction
178 Multiple Thread (SIMT) model, because a programmer accesses
179 the cores by the intermediate of threads. In the CUDA model, all cores
180 execute the same set of instructions but with different data. This model has
181 similarities with the vector programming model proposed for vector machines through
182 the 1970s and into the 90s, notably the various Cray platforms. On the CUDA
183 architecture, the performance is led by the use of a huge number of threads
184 (from thousands up to millions). The particularity of the model is that there
185 is no context switching as in CPUs and each thread has its own registers. In
186 practice, threads are executed by SM and gathered into groups of 32
187 threads, called warps. Each SM alternatively executes
188 active warps and warps becoming temporarily inactive due to waiting of data
189 (as shown in Figure~\ref{ch1:fig:latency_throughput}).
192 \centerline{\includegraphics[scale=0.65]{Chapters/chapter1/figures/scalability.pdf}}
193 \caption{Scalability of GPU.}
194 \label{ch1:fig:scalability}
197 The key to scalability in the CUDA model is the use of a huge number of threads.
198 In practice, threads are gathered not only in warps but also in thread blocks. A
199 thread block is executed by only one SM and it cannot migrate. The typical size of
200 a thread block is a power of two (for example, 64, 128, 256, or 512).
204 In this case, without changing anything inside a CUDA code, it is possible to
205 run code with a small CUDA device or the best performing Tesla CUDA cards.
206 Blocks are executed in any order depending on the number of SMs available. So
207 the programmer must conceive code having this issue in mind. This
208 independence between thread blocks provides the scalability of CUDA codes.
213 A kernel is a function which contains a block of instructions that are executed
214 by the threads of a GPU. When the problem considered is a two-dimensional or three-dimensional problem, it is possible to group thread blocks into a grid. In
215 practice, the number of thread blocks and the size of thread blocks are given as
216 parameters to each kernel. Figure~\ref{ch1:fig:scalability} illustrates an
217 example of a kernel composed of 8 thread blocks. Then this kernel is executed on
218 a small device containing only 2 SMs. {\bf RELIRE} So in this case, blocks are executed 2
219 by 2 in any order. If the kernel is executed on a larger CUDA device containing
220 4 SMs, blocks are executed 4 by 4 simultaneously. The execution times should be
221 approximately twice faster in the latter case. Of course, that depends on other
222 parameters that will be described later (in this chapter and other chapters).
225 Thread blocks provide a way to cooperation in the sense that threads of the same
226 block cooperatively load and store blocks of memory they all
227 use. Synchronizations of threads in the same block are possible (but not between
228 threads of different blocks). Threads of the same block can also share results
229 in order to compute a single result. In Chapter~\ref{chapter2}, some examples
233 \section{Memory hierarchy}
235 The memory hierarchy of GPUs\index{memory~hierarchy} is different from that of CPUs. In practice, there are registers\index{memory~hierarchy!registers}, local
236 memory\index{memory~hierarchy!local~memory}, shared
237 memory\index{memory~hierarchy!shared~memory}, cache
238 memory\index{memory~hierarchy!cache~memory}, and global
239 memory\index{memory~hierarchy!global~memory}.
242 As previously mentioned each thread can access its own registers. It is
243 important to keep in mind that the number of registers per block is limited. On
244 recent cards, this number is limited to 64Kb per SM. Access to registers is
245 very fast, so it is a good idea to use them whenever possible.
247 Likewise each thread can access local memory which, in practice, is much slower
248 than registers. Local memory is automatically used by the compiler when all the
249 registers are occupied. So the best idea is to optimize the use of registers
250 even if this involves reducing the number of threads per block.
252 \begin{figure}[hbtp!]
253 \centerline{\includegraphics[scale=0.60]{Chapters/chapter1/figures/memory_hierarchy.pdf}}
254 \caption{Memory hierarchy of a GPU.}
255 \label{ch1:fig:memory_hierarchy}
260 Shared memory allows cooperation between threads of the same block. This kind
261 of memory is fast but it needs to be manipulated manually and its size is
262 limited. It is accessible during the execution of a kernel. So the idea is
263 to fill the shared memory at the start of the kernel with global data that are
264 used very frequently, then threads can access it for their computation. Threads
265 can obviously change the content of this shared memory either with computation
266 or by loading other data and they can store its content in the global memory. So
267 shared memory can be seen as a cache memory manageable manually. This
268 obviously requires an effort from the programmer.
270 On recent cards, the programmer may decide what amount of cache memory and
271 shared memory is attributed to a kernel. The cache memory is an L1 cache which is
272 directly managed by the GPU. Sometimes, this cache provides very efficient
273 result and sometimes the use of shared memory is a better solution.
278 Figure~\ref{ch1:fig:memory_hierarchy} illustrates the memory hierarchy of a
279 GPU. Threads are represented on the top of the figure. They can have access to their
280 own registers and their local memory. Threads of the same block can access
281 the shared memory of that block. The cache memory is not represented here but it
282 is local to a thread. Then each block can access the global memory of the
287 In this chapter, a brief presentation of the video card, which has later been
288 used to perform computation, has been given. The architecture of a GPU has been
289 illustrated focusing on the particularity of GPUs in terms of parallelism, memory
290 latency, and threads. In order to design an efficient algorithm for GPU, it is
291 essential to keep all these parameters in mind.
294 \putbib[Chapters/chapter1/biblio]
