\begin{figure}[!h]
\centering
\includegraphics[width=10cm]{Chapters/chapter10/figures/Reduc3.pdf}
-\caption{Example of a parallel reduction at block level (courtesy NVIDIA).}
+\caption{Example of a parallel reduction at block level. (Courtesy NVIDIA).}
\label{chXXX:fig:reduc}
\end{figure}
*, *, *, 10, *, *}
\end{lstlisting}
- \subsubsection*{Hybrid (HYB)\index{compressed storage format!HYB}} The HYB format heuristically computes a value $K$ and stores $K$ nonzeros per rows in the ELL format. When a row has more than $K$ non-zeros, the trailing nonzeros are stored in COO. This design decreases the storage overhead due to ELL padding elements and thus improves the overall performance.
+ \subsubsection*{Hybrid (HYB)\index{compressed storage format!HYB}} The HYB format heuristically computes a value $K$ and stores $K$ nonzeros per rows in the ELL format. When a row has more than $K$ non zeros, the trailing nonzeros are stored in COO. This design decreases the storage overhead due to ELL padding elements and thus improves the overall performance.
+\pagebreak
\begin{lstlisting}[caption={}]
hyb.nnz_per_row = 2
hyb.ell.col_index = {2, 1, 1, 0, 2, 0, *, 4, 3, 2, *, 5}
\begin{figure}[t]
\centering
\includegraphics[height=5cm]{Chapters/chapter19/fig/scoo.pdf}
- \caption{Example of the memory access pattern for a $6 \times 6$ matrix stored in Sliced COO format (Slice Size = 3 rows).}
+ \caption{Example of the memory access pattern for a $6 \times 6$ matrix stored in sliced COO format (slice size = 3 rows).}
\label{fig:scoo-1}
\end{figure}
\hline
\end{tabular}
\end{center}
-\caption{Overview of hardware used in the experiments}
+\caption{Overview of hardware used in the experiments.}
\label{table:hardware}
\end{table}
\hline
\end{tabular}
- \caption{Performance of SpMV on RSA-170 matrix}
+ \caption{Performance of SpMV on RSA-170 matrix.}
\label{table:rsa170}
\end{table}