2 \documentclass[10pt, peerreview, compsocconf]{IEEEtran}
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32 %% \author{\IEEEauthorblockN{Authors Name/s per 1st Affiliation (Author)}
33 %% \IEEEauthorblockA{line 1 (of Affiliation): dept. name of organization\\
34 %% line 2: name of organization, acronyms acceptable\\
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47 \title{A new approach based on least square methods to estimate in real time cantilevers deflection with a FPGA}
48 \author{\IEEEauthorblockN{Raphaël Couturier\IEEEauthorrefmark{1}, Stéphane Domas\IEEEauthorrefmark{1}, Gwenhaël Goavec-Merou\IEEEauthorrefmark{2} and Michel Lenczner\IEEEauthorrefmark{2}}
49 \IEEEauthorblockA{\IEEEauthorrefmark{1}FEMTO-ST, DISC, University of Franche-Comte, Belfort, France\\
50 \{raphael.couturier,stephane.domas\}@univ-fcomte.fr}
51 \IEEEauthorblockA{\IEEEauthorrefmark{2}FEMTO-ST, Time-Frequency, University of Franche-Comte, Besançon, France\\
52 \{michel.lenczner@utbm.fr,gwenhael.goavec@trabucayre.com}
66 Atomics force microscope (AFM) provide high resolution images of surfaces. In
67 this paper, we focus our attention on an interferometry method to estimate the
68 cantilevers deflection. The initial method was based on splines to determine
69 the phase of interference fringes, and thus the deflection. Computations were
70 performed on a PC with LabView. Here, we propose a new approach based on the
71 least square methods and its implementation that we have developed on a FPGA,
72 using the pipelining technique. Simulations and real tests showed us that this
73 implementation is very efficient and should allow us to control a cantilevers
80 FPGA, cantilever, interferometry.
84 \IEEEpeerreviewmaketitle
86 \section{Introduction}
88 Cantilevers are used inside atomic force microscopes (AFM) which provide high
89 resolution images of surfaces. Several techniques have been used to measure the
90 displacement of cantilevers in literature. For example, it is possible to
91 determine accurately the deflection with different mechanisms.
92 In~\cite{CantiPiezzo01}, authors used piezoresistor integrated into the
93 cantilever. Nevertheless this approach suffers from the complexity of the
94 microfabrication process needed to implement the sensor in the cantilever.
95 In~\cite{CantiCapacitive03}, authors have presented a cantilever mechanism
96 based on capacitive sensing. This kind of technique also involves to instrument
97 the cantilever which results in a complex fabrication process.
99 In this paper our attention is focused on a method based on interferometry to
100 measure cantilevers' displacements. In this method cantilevers are illuminated
101 by an optic source. The interferometry produces fringes on each cantilever which
102 enables us to compute the cantilever displacement. In order to analyze the
103 fringes a high speed camera is used. Images need to be processed quickly and
104 then an estimation method is required to determine the displacement of each
105 cantilever. In~\cite{AFMCSEM11}, authors have used an algorithm based on spline
106 to estimate the cantilevers' positions.
108 The overall process gives accurate results but all the computations are
109 performed on a standard computer using LabView. Consequently, the main drawback
110 of this implementation is that the computer is a bottleneck. In this paper we
111 propose to use a method based on least squares and to implement all the
112 computation on a FPGA.
114 The remainder of the paper is organized as follows. Section~\ref{sec:measure}
115 describes more precisely the measurement process. Our solution based on the
116 least square method and the implementation on FPGA is presented in
117 Section~\ref{sec:solus}. Experimentations are described in
118 Section~\ref{sec:results}. Finally a conclusion and some perspectives are
125 \section{Measurement principles}
128 \subsection{Architecture}
132 In order to develop simple, cost effective and user-friendly cantilever arrays,
133 authors of ~\cite{AFMCSEM11} have developed a system based on
134 interferometry. In opposition to other optical based systems, using a laser beam
135 deflection scheme and sensitive to the angular displacement of the cantilever,
136 interferometry is sensitive to the optical path difference induced by the
137 vertical displacement of the cantilever.
139 The system built by these authors is based on a Linnick
140 interferometer~\cite{Sinclair:05}. It is illustrated in Figure~\ref{fig:AFM}.
141 A laser diode is first split (by the splitter) into a reference beam and a
142 sample beam that reach the cantilever array. In order to be able to move the
143 cantilever array, it is mounted on a translation and rotational hexapod stage
144 with five degrees of freedom. The optical system is also fixed to the stage.
145 Thus, the cantilever array is centered in the optical system which can be
146 adjusted accurately. The beam illuminates the array by a microscope objective
147 and the light reflects on the cantilevers. Likewise the reference beam reflects
148 on a movable mirror. A CMOS camera chip records the reference and sample beams
149 which are recombined in the beam splitter and the interferogram. At the
150 beginning of each experiment, the movable mirror is fitted manually in order to
151 align the interferometric fringes approximately parallel to the cantilevers.
152 When cantilevers move due to the surface, the bending of cantilevers produce
153 movements in the fringes that can be detected with the CMOS camera. Finally the
154 fringes need to be analyzed. In~\cite{AFMCSEM11}, authors used a LabView program
155 to compute the cantilevers' deflections from the fringes.
159 \includegraphics[width=\columnwidth]{AFM}
161 \caption{schema of the AFM}
166 %% image tirée des expériences.
168 \subsection{Cantilever deflection estimation}
173 \includegraphics[width=\columnwidth]{lever-xp}
175 \caption{Portion of an image picked by the camera}
179 As shown on image \ref{fig:img-xp}, each cantilever is covered by
180 several interferometric fringes. The fringes will distort when
181 cantilevers are deflected. Estimating the deflection is done by
182 computing this distortion. For that, authors of \cite{AFMCSEM11}
183 proposed a method based on computing the phase of the fringes, at the
184 base of each cantilever, near the tip, and on the base of the
185 array. They assume that a linear relation binds these phases, which
186 can be used to "unwrap" the phase at the tip and to determine the deflection.\\
188 More precisely, segments of pixels are extracted from images taken by
189 the camera. These segments are large enough to cover several
190 interferometric fringes. As said above, they are placed at the base
191 and near the tip of the cantilevers. They are called base profile and
192 tip profile in the following. Furthermore, a reference profile is
193 taken on the base of the cantilever array.
195 The pixels intensity $I$ (in gray level) of each profile is modelized by:
199 I(x) = ax+b+A.cos(2\pi f.x + \theta)
202 where $x$ is the position of a pixel in its associated segment.
204 The global method consists in two main sequences. The first one aims
205 to determine the frequency $f$ of each profile with an algorithm based
206 on spline interpolation (see section \ref{sec:algo-spline}). It also
207 computes the coefficient used for unwrapping the phase. The second one
208 is the acquisition loop, during which images are taken at regular time
209 steps. For each image, the phase $\theta$ of all profiles is computed
210 to obtain, after unwrapping, the deflection of
211 cantilevers. Originally, this computation was also done with an
212 algorithm based on spline. This article proposes a new version based
213 on a least square method.
215 \subsection{Design goals}
218 The main goal is to implement a computing unit to estimate the
219 deflection of about $10\times10$ cantilevers, faster than the stream of
220 images coming from the camera. The accuracy of results must be close
221 to the maximum precision ever obtained experimentally on the
222 architecture, i.e. 0.3nm. Finally, the latency between an image
223 entering in the unit and the deflections must be as small as possible
224 (NB: future works plan to add some control on the cantilevers).\\
226 If we put aside some hardware issues like the speed of the link
227 between the camera and the computation unit, the time to deserialize
228 pixels and to store them in memory, ... the phase computation is
229 obviously the bottle-neck of the whole process. For example, if we
230 consider the camera actually in use, an exposition time of 2.5ms for
231 $1024\times 1204$ pixels seems the minimum that can be reached. For
232 100 cantilevers, if we neglect the time to extract pixels, it implies
233 that computing the deflection of a single
234 cantilever should take less than 25$\mu$s, thus 12.5$\mu$s by phase.\\
236 In fact, this timing is a very hard constraint. Let us consider a very
237 small program that initializes twenty million of doubles in memory
238 and then does 1,000,000 cumulated sums on 20 contiguous values
239 (experimental profiles have about this size). On an intel Core 2 Duo
240 E6650 at 2.33GHz, this program reaches an average of 155Mflops.
242 %%Itimplies that the phase computation algorithm should not take more than
243 %%$155\times 12.5 = 1937$ floating operations. For integers, it gives $3000$ operations.
245 Obviously, some cache effects and optimizations on
246 huge amount of computations can drastically increase these
247 performances: peak efficiency is about 2.5Gflops for the considered
248 CPU. But this is not the case for phase computation that used only a few
251 In order to evaluate the original algorithm, we translated it in C
252 language. As stated before, for 20 pixels, it does about 1,550
253 operations, thus an estimated execution time of $1,550/155
254 =$10$\mu$s. For a more realistic evaluation, we constructed a file of
255 1Mo containing 200 profiles of 20 pixels, equally scattered. This file
256 is equivalent to an image stored in a device file representing the
257 camera. We obtained an average of 10.5$\mu$s by profile (including I/O
258 accesses). It is under our requirements but close to the limit. In
259 case of an occasional load of the system, it could be largely
260 overtaken. A solution would be to use a real-time operating system but
261 another one to search for a more efficient algorithm.
263 But the main drawback is the latency of such a solution: since each
264 profile must be treated one after another, the deflection of 100
265 cantilevers takes about $200\times 10.5 = 2.1$ms, which is inadequate
266 for an efficient control. An obvious solution is to parallelize the
267 computations, for example on a GPU. Nevertheless, the cost of transferring
268 profile in GPU memory and of taking back results would be prohibitive
269 compared to computation time. It is certainly more efficient to
270 pipeline the computation. For example, supposing that 200 profiles of
271 20 pixels can be pushed sequentially in the pipelined unit cadenced at
272 a 100MHz (i.e. a pixel enters in the unit each 10ns), all profiles
273 would be treated in $200\times 20\times 10.10^{-9} =$ 40$\mu$s plus
274 the latency of the pipeline. This is about 500 times faster than
277 For these reasons, a FPGA as the computation unit is the best choice
278 to achieve the required performance. Nevertheless, passing from
279 a C code to a pipelined version in VHDL is not obvious at all. As
280 explained in the next section, it can even be impossible because of
281 some hardware constraints specific to FPGAs.
284 \section{Proposed solution}
287 Project Oscar aims to provide a hardware and software architecture to estimate
288 and control the deflection of cantilevers. The hardware part consists in a
289 high-speed camera, linked on an embedded board hosting FPGAs. In this way, the
290 camera output stream can be pushed directly into the FPGA. The software part is
291 mostly the VHDL code that deserializes the camera stream, extracts profile and
292 computes the deflection. Before focusing on our work to implement the phase
293 computation, we give some general information about FPGAs and the board we use.
297 A field-programmable gate array (FPGA) is an integrated circuit designed to be
298 configured by the customer. FGPAs are composed of programmable logic components,
299 called configurable logic blocks (CLB). These blocks mainly contain look-up
300 tables (LUT), flip/flops (F/F) and latches, organized in one or more slices
301 connected together. Each CLB can be configured to perform simple (AND, XOR, ...)
302 or complex combinational functions. They are interconnected by reconfigurable
303 links. Modern FPGAs contain memory elements and multipliers which enable to
304 simplify the design and to increase the performance. Nevertheless, all other
305 complex operations, like division, trigonometric functions, $\ldots$ are not
306 available and must be done by configuring a set of CLBs. Since this
307 configuration is not obvious at all, it can be done via a framework, like
308 ISE~\cite{ISE}. Such a software can synthetize a design written in a hardware
309 description language (HDL), map it onto CLBs, place/route them for a specific
310 FPGA, and finally produce a bitstream that is used to configure the FPGA. Thus,
311 from the developer's point of view, the main difficulty is to translate an
312 algorithm in HDL code, taking into account FPGA resources and constraints like
313 clock signals and I/O values that drive the FPGA.
315 Indeed, HDL programming is very different from classic languages like
316 C. A program can be seen as a state-machine, manipulating signals that
317 evolve from state to state. Moreover, HDL instructions can executed
318 concurrently. Basic logic operations are used to aggregate signals to
319 produce new states and assign it to another signal. States are mainly
320 expressed as arrays of bits. Fortunately, libraries propose some
321 higher levels representations like signed integers, and arithmetic
324 Furthermore, even if FPGAs are cadenced more slowly than classic
325 processors, they can perform pipeline as well as parallel
326 operations. A pipeline consists in cutting a process in a sequence of
327 small tasks, taking the same execution time. It accepts a new data at
328 each clock top, thus, after a known latency, it also provides a result
329 at each clock top. However, using a pipeline consumes more logics
330 since the components of a task are not reusable by another
331 one. Nevertheless it is probably the most efficient technique on
332 FPGA. Because of its architecture, it is also very easy to process
333 several data concurrently. Whenever possible, the best performance
334 is reached using parallelism to handle simultaneously several
335 pipelines in order to handle multiple data streams.
337 \subsection{The board}
339 The board we use is designed by the Armadeus company, under the name
340 SP Vision. It consists in a development board hosting a i.MX27 ARM
341 processor (from Freescale). The board includes all classical
342 connectors: USB, Ethernet, ... A Flash memory contains a Linux kernel
343 that can be launched after booting the board via u-Boot.
345 The processor is directly connected to a Spartan3A FPGA (from Xilinx)
346 via its special interface called WEIM. The Spartan3A is itself
347 connected to a Spartan6 FPGA. Thus, it is possible to develop programs
348 that communicate between i.MX and Spartan6, using Spartan3 as a
349 tunnel. By default, the WEIM interface provides a clock signal at
350 100MHz that is connected to dedicated FPGA pins.
352 The Spartan6 is an LX100 version. It has 15822 slices, each slice
353 containing 4 LUTs and 8 flip/flops. It is equivalent to 101261 logic
354 cells. There are 268 internal block RAM of 18Kbits, and 180 dedicated
355 multiply-adders (named DSP48), which is largely enough for our
358 Some I/O pins of Spartan6 are connected to two $2\times 17$ headers
359 that can be used as user wants. For the project, they will be
360 connected to the interface card of the camera.
362 \subsection{Considered algorithms}
364 Two solutions have been studied to achieve phase computation. The
365 original one, proposed by A. Meister and M. Favre, is based on
366 interpolation by splines. It allows to compute frequency and
367 phase. The second one, detailed in this article, is based on a
368 classical least square method which supposes that the frequency is already
371 \subsubsection{Spline algorithm (SPL)}
372 \label{sec:algo-spline}
373 Let us consider a profile $P$, that is a segment of $M$ pixels with an
374 intensity in gray levels. Let us call $I(x)$ the intensity of profile in $x
377 At first, only $M$ values of $I$ are known, for $x = 0, 1,
378 \ldots,M-1$. A normalization allows to scale known intensities into
379 $[-1,1]$. We compute splines that fit at best these normalized
380 intensities. Splines are used to interpolate $N = k\times M$ points
381 (typically $k=4$ is sufficient), within $[0,M[$. Let $x^s$ be the
382 coordinates of these $N$ points and $I^s$ their intensities.
384 In order to have the frequency, the mean line $a.x+b$ (see equation \ref{equ:profile}) of $I^s$ is
385 computed. Finding intersections of $I^s$ and this line allows us to obtain
386 the period and thus the frequency.
388 The phase is computed via the equation:
390 \theta = atan \left[ \frac{\sum_{i=0}^{N-1} sin(2\pi f x^s_i) \times I^s(x^s_i)}{\sum_{i=0}^{N-1} cos(2\pi f x^s_i) \times I^s(x^s_i)} \right]
393 Two things can be noticed:
395 \item the frequency could also be obtained using the derivates of
396 spline equations, which only implies to solve quadratic equations.
397 \item frequency of each profile is computed only once, before the
398 acquisition loop. Thus, $sin(2\pi f x^s_i)$ and $cos(2\pi f x^s_i)$
399 could also be computed before the loop, which would lead to a much faster
400 computation of $\theta$.
403 \subsubsection{Least square algorithm (LSQ)}
405 Assuming that we compute the phase during the acquisition loop,
406 equation \ref{equ:profile} has only 4 parameters: $a, b, A$, and
407 $\theta$, $f$ and $x$ being already known. Since $I$ is non-linear, a
408 least square method based on a Gauss-newton algorithm can be used to
409 determine these four parameters. Since it is an iterative process
410 ending with a convergence criterion, it is obvious that it is not
411 particularly adapted to our design goals.
413 Fortunately, it is quite simple to reduce the number of parameters to
414 only $\theta$. Let $x^p$ be the coordinates of pixels in a segment of
415 size $M$. Thus, $x^p = 0, 1, \ldots, M-1$. Let $I(x^p)$ be their
416 intensity. Firstly, we "remove" the slope by computing:
418 \[I^{corr}(x^p) = I(x^p) - a.x^p - b\]
420 Since linear equation coefficients are searched, a classical least
421 square method can be used to determine $a$ and $b$:
423 \[a = \frac{covar(x^p,I(x^p))}{var(x^p)} \]
425 Assuming an overlined symbol means an average, then:
427 \[b = \overline{I(x^p)} - a.\overline{{x^p}}\]
429 Let $A$ be the amplitude of $I^{corr}$, i.e.
431 \[A = \frac{max(I^{corr}) - min(I^{corr})}{2}\]
433 Then, the least square method to find $\theta$ is reduced to search the minimum of:
435 \[\sum_{i=0}^{M-1} \left[ cos(2\pi f.i + \theta) - \frac{I^{corr}(i)}{A} \right]^2\]
437 It is equivalent to derivating this expression and to solving the following equation:
440 %\begin{eqnarray*}{l}
441 $$2\left[ cos\theta \sum_{i=0}^{M-1} I^{corr}(i).sin(2\pi f.i) \right.$$
442 $$\left. + sin\theta \sum_{i=0}^{M-1} I^{corr}(i).cos(2\pi f.i)\right]- $$
443 $$ A\left[ cos2\theta \sum_{i=0}^{M-1} sin(4\pi f.i) + sin2\theta \sum_{i=0}^{M-1} cos(4\pi f.i)\right] = 0$$
447 Several points can be noticed:
449 \item As in the spline method, some parts of this equation can be
450 computed before the acquisition loop. It is the case of sums that do
451 not depend on $\theta$:
453 \[ \sum_{i=0}^{M-1} sin(4\pi f.i), \sum_{i=0}^{M-1} cos(4\pi f.i) \]
455 \item Lookup tables for $sin(2\pi f.i)$ and $cos(2\pi f.i)$ can also be
458 \item The simplest method to find the good $\theta$ is to discretize
459 $[-\pi,\pi]$ in $nb_s$ steps, and to search which step leads to the
460 result closest to zero. Hence, three other lookup tables can
461 also be computed before the loop:
463 \[ sin \theta, cos \theta, \]
465 \[ \left[ cos 2\theta \sum_{i=0}^{M-1} sin(4\pi f.i) + sin 2\theta \sum_{i=0}^{M-1} cos(4\pi f.i)\right] \]
467 \item This search can be very fast using a dichotomous process in $log_2(nb_s)$
471 Finally, this is synthetized in an algorithm (called LSQ in the following) in two parts, one before and one during the acquisition loop:
472 \begin{algorithm}[htbp]
473 \caption{LSQ algorithm - before acquisition loop.}
474 \label{alg:lsq-before}
476 $M \leftarrow $ number of pixels of the profile\\
477 I[] $\leftarrow $ intensity of pixels\\
478 $f \leftarrow $ frequency of the profile\\
479 $s4i \leftarrow \sum_{i=0}^{M-1} sin(4\pi f.i)$\\
480 $c4i \leftarrow \sum_{i=0}^{M-1} cos(4\pi f.i)$\\
481 $nb_s \leftarrow $ number of discretization steps of $[-\pi,\pi]$\\
483 \For{$i=0$ to $nb_s $}{
484 $\theta \leftarrow -\pi + 2\pi\times \frac{i}{nb_s}$\\
485 lut$_s$[$i$] $\leftarrow sin \theta$\\
486 lut$_c$[$i$] $\leftarrow cos \theta$\\
487 lut$_A$[$i$] $\leftarrow cos 2 \theta \times s4i + sin 2 \theta \times c4i$\\
488 lut$_{sfi}$[$i$] $\leftarrow sin (2\pi f.i)$\\
489 lut$_{cfi}$[$i$] $\leftarrow cos (2\pi f.i)$\\
493 \begin{algorithm}[htbp]
494 \caption{LSQ algorithm - during acquisition loop.}
495 \label{alg:lsq-during}
497 $\bar{x} \leftarrow \frac{M-1}{2}$\\
498 $\bar{y} \leftarrow 0$, $x_{var} \leftarrow 0$, $xy_{covar} \leftarrow 0$\\
499 \For{$i=0$ to $M-1$}{
500 $\bar{y} \leftarrow \bar{y} + $ I[$i$]\\
501 $x_{var} \leftarrow x_{var} + (i-\bar{x})^2$\\
503 $\bar{y} \leftarrow \frac{\bar{y}}{M}$\\
504 \For{$i=0$ to $M-1$}{
505 $xy_{covar} \leftarrow xy_{covar} + (i-\bar{x}) \times (I[i]-\bar{y})$\\
507 $slope \leftarrow \frac{xy_{covar}}{x_{var}}$\\
508 $start \leftarrow y_{moy} - slope\times \bar{x}$\\
509 \For{$i=0$ to $M-1$}{
510 $I[i] \leftarrow I[i] - start - slope\times i$\\
513 $I_{max} \leftarrow max_i(I[i])$, $I_{min} \leftarrow min_i(I[i])$\\
514 $amp \leftarrow \frac{I_{max}-I_{min}}{2}$\\
516 $Is \leftarrow 0$, $Ic \leftarrow 0$\\
517 \For{$i=0$ to $M-1$}{
518 $Is \leftarrow Is + I[i]\times $ lut$_{sfi}$[$i$]\\
519 $Ic \leftarrow Ic + I[i]\times $ lut$_{cfi}$[$i$]\\
522 $\delta \leftarrow \frac{nb_s}{2}$, $b_l \leftarrow 0$, $b_r \leftarrow \delta$\\
523 $v_l \leftarrow -2.I_s - amp.$lut$_A$[$b_l$]\\
525 \While{$\delta >= 1$}{
527 $v_r \leftarrow 2.[ Is.$lut$_c$[$b_r$]$ + Ic.$lut$_s$[$b_r$]$ ] - amp.$lut$_A$[$b_r$]\\
529 \If{$!(v_l < 0$ and $v_r >= 0)$}{
530 $v_l \leftarrow v_r$ \\
531 $b_l \leftarrow b_r$ \\
533 $\delta \leftarrow \frac{\delta}{2}$\\
534 $b_r \leftarrow b_l + \delta$\\
536 \uIf{$!(v_l < 0$ and $v_r >= 0)$}{
537 $v_l \leftarrow v_r$ \\
538 $b_l \leftarrow b_r$ \\
539 $b_r \leftarrow b_l + 1$\\
540 $v_r \leftarrow 2.[ Is.$lut$_c$[$b_r$]$ + Ic.$lut$_s$[$b_r$]$ ] - amp.$lut$_A$[$b_r$]\\
543 $b_r \leftarrow b_l + 1$\\
546 \uIf{$ abs(v_l) < v_r$}{
547 $b_{\theta} \leftarrow b_l$ \\
550 $b_{\theta} \leftarrow b_r$ \\
552 $\theta \leftarrow \pi\times \left[\frac{2.b_{ref}}{nb_s}-1\right]$\\
556 \subsubsection{Comparison}
558 We compared the two algorithms on the base of three criteria:
560 \item precision of results on a cosines profile, distorted by noise,
561 \item number of operations,
562 \item complexity of implementating an FPGA version.
565 For the first item, we produced a matlab version of each algorithm,
566 running with double precision values. The profile was generated for
567 about 34000 different values of period ($\in [3.1, 6.1]$, step = 0.1),
568 phase ($\in [-3.1 , 3.1]$, step = 0.062) and slope ($\in [-2 , 2]$,
569 step = 0.4). For LSQ, $nb_s = 1024$, which leads to a maximal error of
570 $\frac{\pi}{1024}$ on phase computation. Current A. Meister and
571 M. Favre's experiments show a ratio of 50 between the variation of a phase and
572 the deflection of a lever. Thus, the maximal error due to
573 discretization corresponds to an error of 0.15nm on the lever
574 deflection, which is smaller than the best precision they achieved,
577 For each test, we add some noise to the profile: each group of two
578 pixels has its intensity added to a random number picked in $[-N,N]$
579 (NB: it should be noticed that picking a new value for each pixel does
580 not distort enough the profile). The absolute error on the result is
581 evaluated by comparing the difference between the reference and
582 computed phase, out of $2\pi$, expressed in percentage. That is: $err =
583 100\times \frac{|\theta_{ref} - \theta_{comp}|}{2\pi}$.
585 Table \ref{tab:algo_prec} gives the maximum and average error for both
586 algorithms and increasing values of $N$.
590 \begin{tabular}{|c|c|c|c|c|}
592 & \multicolumn{2}{c|}{SPL} & \multicolumn{2}{c|}{LSQ} \\ \cline{2-5}
593 noise & max. err. & aver. err. & max. err. & aver. err. \\ \hline
594 0 & 2.46 & 0.58 & 0.49 & 0.1 \\ \hline
595 2.5 & 2.75 & 0.62 & 1.16 & 0.22 \\ \hline
596 5 & 3.77 & 0.72 & 2.47 & 0.41 \\ \hline
597 7.5 & 4.72 & 0.86 & 3.33 & 0.62 \\ \hline
598 10 & 5.62 & 1.03 & 4.29 & 0.81 \\ \hline
599 15 & 7.96 & 1.38 & 6.35 & 1.21 \\ \hline
600 30 & 17.06 & 2.6 & 13.94 & 2.45 \\ \hline
603 \caption{Error (in \%) for cosines profiles, with noise.}
604 \label{tab:algo_prec}
608 These results show that the two algorithms are very close, with a
609 slight advantage for LSQ. Furthermore, both behave very well against
610 noise. Assuming the experimental ratio of 50 (see above), an error of
611 1 percent on the phase corresponds to an error of 0.5nm on the lever
612 deflection, which is very close to the best precision.
614 Obviously, it is very hard to predict which level of noise will be
615 present in real experiments and how it will distort the
616 profiles. Nevertheless, we can see on figure \ref{fig:noise20} the
617 profile with $N=10$ that leads to the biggest error. It is a bit
618 distorted, with pikes and straight/rounded portions, and relatively
619 close to experiments. Figure \ref{fig:noise60}
620 shows a sample of worst profile for $N=30$. It is completely distorted,
621 largely beyond the worst experimental ones.
625 \includegraphics[width=\columnwidth]{intens-noise20}
627 \caption{Sample of worst profile for N=10}
633 \includegraphics[width=\columnwidth]{intens-noise60}
635 \caption{Sample of worst profile for N=30}
639 The second criterion is relatively easy to estimate for LSQ and harder
640 for SPL because of $atan$ operation. In both cases, it is proportional
641 to the numbers of pixels $M$. For LSQ, it also depends on $nb_s$ and for
642 SPL on $N = k\times M$, i.e. the number of interpolated points.
644 We assume that $M=20$, $nb_s=1024$, $k=4$, all possible parts are
645 already in lookup tables and a limited set of operations (+, -, *, /,
646 $<$, $>$) is taken into account. Translating both algorithms in C code, we
647 obtain about 430 operations for LSQ and 1,550 (plus a few tenth for
648 $atan$) for SPL. This result is largely in favor of LSQ. Nevertheless,
649 considering the total number of operations is not really pertinent for
650 an FPGA implementation: it mainly depends on the type of operations
652 ordering. The final decision is thus driven by the third criterion.\\
654 The Spartan 6 used in our architecture has a hard constraint: it has no built-in
655 floating point units. Obviously, it is possible to use some existing
656 "black-boxes" for double precision operations. But they have quite a long
657 latency. It is much simpler to exclusively use integers, with a quantization of
658 all double precision values. Obviously, this quantization should not decrease
659 too much the precision of results. Furthermore, it should not lead to a design
660 with a huge latency because of operations that could not complete during a
661 single or few clock cycles. Divisions fall into that category and, moreover,
662 they need a varying number of clock cycles to complete. Even multiplications can
663 be a problem: a DSP48 takes inputs of 18 bits maximum. For larger multiplications,
664 several DSP must be combined, increasing the latency.
666 Nevertheless, the hardest constraint does not come from the FPGA characteristics
667 but from the algorithms. Their VHDL implementation will be efficient only if
668 they can be fully (or near) pipelined. Thus, the choice is quickly made: only a
669 small part of SPL can be pipelined. Indeed, the computation of spline
670 coefficients implies to solve a tridiagonal system $A.m = b$. Values in $A$ and
671 $b$ can be computed from incoming pixels intensity but after, the back-solve
672 starts with the latest values, which breaks the pipeline. Moreover, SPL relies
673 on interpolating far more points than profile size. Thus, the end of SPL works
674 on a larger amount of data than at the beginning, which also breaks the pipeline.
676 LSQ has not this problem: all parts except the dichotomial search work on the
677 same amount of data, i.e. the profile size. Furthermore, LSQ needs less
678 operations than SPL, implying a smaller output latency. Consequently, it is the
679 best candidate for phase computation. Nevertheless, obtaining a fully pipelined
680 version supposes that operations of different parts complete in a single clock
681 cycle. It is the case for simulations but it completely fails when mapping and
682 routing the design on the Spartan6. Thus, extra-latency is generated and
683 there must be idle times between two profiles entering into the pipeline.
685 %%Before obtaining the least bitstream, the crucial question is: how to
686 %%translate the C code the LSQ into VHDL ?
689 %\subsection{VHDL design paradigms}
691 \section{Experimental tests}
693 %In this section we explain what we have done yet. Until now, we could not perform
694 %real experiments since we just have received the FGPA board. Nevertheless, we
695 %will include real experiments in the final version of this paper.
697 \subsection{VHDL implementation}
699 From the LSQ algorithm, we have written a C program that uses only
700 integer values. We use a very simple quantization by multiplying
701 double precision values by a power of two, keeping the integer
702 part. For example, all values stored in lut$_s$, lut$_c$, $\ldots$ are
703 scaled by 1,024. Since LSQ also computes average, variance, ... to
704 remove the slope, the result of implied Euclidean divisions may be
705 relatively wrong. To avoid that, we also scale the pixel intensities
706 by a power of two. Furthermore, assuming $nb_s$ is fixed, these
707 divisions have a known denominator. Thus, they can be replaced by
708 their multiplication/shift counterpart. Finally, all other
709 multiplications or divisions by a power of two have been replaced by
710 left or right bit shifts. Thus, the code only contains
711 additions, subtractions and multiplications of signed integers, which
712 are perfectly adapted to FGPAs.
714 As mentioned above, hardware constraints have a great influence on the VHDL
715 implementation. Consequently, we searched the maximum value of each variable as
716 a function of the different scale factors and the size of profiles, which gives
717 their maximum size in bits. That size determines the maximum scale factors that
718 allow to use the least possible RAMs and DSPs. Actually, we implemented our
719 algorithm with this maximum size but current works study the impact of
720 quantization on the results precision and design complexity. We have compared
721 the result of the LSQ version using integers and doubles and observed that the
722 precision of both were similar.
724 Then we built two versions of VHDL codes: one directly by hand coding
725 and the other with Matlab using the Simulink HDL coder
726 feature~\cite{HDLCoder}. Although the approach is completely different
727 we obtained VHDL codes that are quite comparable. Each approach has
728 advantages and drawbacks. Roughly speaking, hand coding provides
729 beautiful and much better structured code while Simulink enables us to
730 produce a code faster. In terms of throughput and latency,
731 simulations show that the two approaches are close with a slight
732 advantage for hand coding. We hope that real experiments will confirm
735 \subsection{Simulation}
737 Before experimental tests on the board, we simulated our two VHDL
738 codes with GHDL and GTKWave (two free tools with linux). For that, we
739 built a testbench based on profiles taken from experimentations and
740 compared the results to values given by the SPL algorithm. Both
741 versions lead to correct results.
743 Our first codes were highly optimized : the pipeline could compute a
744 new phase each 33 cycles and its latency was equal to 95 cycles. Since
745 the Spartan6 is clocked at 100MHz, it implies that estimating the
746 deflection of 100 cantilevers would take about $(95 + 200\times 33).10
747 = 66.95\mu$s, i.e. nearly 15,000 estimations by second.
749 \subsection{Bitstream creation}
751 In order to test our code on the SP Vision board, the design was
752 extended with a component that keeps profiles in RAM, flushes them in
753 the phase computation component and stores its output in another
754 RAM. We also added a wishbone : a component that can "drive" signals
755 to communicate between i.MX and other components. It is mainly used
756 to start to flush profiles and to retrieve the computed phases in RAM.
758 Unfortunately, the first designs could not be placed and route with ISE on the
759 Spartan6 with a 100MHz clock. The main problems came from routing values from
760 RAMs to DSPs and obtaining a result under 10ns. So, we needed to decompose some
761 parts of the pipeline, which adds some cycles. For example, some delays have
762 been introduced between RAMs output and DSPs. Finally, we obtained a bitstream
763 that has a latency of 112 cycles and computes a new phase every 40 cycles. For
764 100 cantilevers, it takes $(112 + 200\times 40).10 = 81.12\mu$s to compute their
767 This bitstream has been successfully tested on the board.
776 \section{Conclusion and perspectives}
777 In this paper we have presented a new method to estimate the
778 cantilevers deflection in an AFM. This method is based on least
779 square methods. We have used quantization to produce an algorithm
780 based exclusively on integer values, which is adapted to a FPGA
781 implementation. We obtained a precision on results similar to the
782 initial version based on splines. Our solution has been implemented
783 with a pipeline technique. Consequently, it enables to handle a new
784 profile image very quickly. Currently we have performed simulations
785 and real tests on a Spartan6 FPGA.
787 In future work, we plan to study the quantization. Then we want to couple our
788 algorithm with a high speed camera and we plan to control the whole AFM system.
790 \bibliographystyle{plain}
791 \bibliography{biblio}