1 Passing now to the second section of the RNG theory and concept part.
2 It contains analyses that been found for the fpga implementations of True RNG.
3 As been defined earlier, TRNG are completely physical generator that use many hardware component and polynomial been produced, where FPGA is one HW support that this survey illustrate all works around it as an accelerator and for security purpose. However, man techniques and HW optimization has been demonstrated are show in this survey, where we can found the use the FPGA component optimized or mixing external component with FPGA or post processing FPGA to generate RNG.
6 \textit{Phase-Locked Loop} or PLL circuit in general is derived by an external clock generator source like quartz or RC circuit, and which can set static or dynamic configuration. A PLL is completely depended of the physical environment like power, temperature or others that cause a very high secure RNG and reduce attacks. the TRNG generator based PLL will use a jitter extractor to generate randomness, wich is a short-term variation of the clock propagation. The most common jitter measurements used by FPGA vendors are period jitter and cycle-to-cycle jitter. The period jitter is defined as the difference between the n-th clock period and the mean clock period. However and in FPGA, a PLL is is based on the size of the clock jitter, the frequency divided by the VCO and the his loop filter bandwidth. Generally, we can find an analog PLL TRNG that extract the "intrinsic jitter" causes by the nois of his VCO for example or a digital PLL generator that use a synchronous/asynchronous Flip-Flop as an extractor.
7 we can find an old implementation in \cite{fischer2003true}, where the authors propose an analysis about extracting randomness from the jitter of an PLL implemented on Altera FPLD. Their studies is based on detecting the jitter by the sampling the reference clock signal ($F_{CLK}$) using a correlated signal synthesized in the PLL ($F_{CLG}$) where $F_{CLG}= \ F_{CLK}(K_{M}/K_{D})$, and the maximum distance between the two clock (CLK,CLG) must be minimum $MAX(\Delta T_{min}) < \sigma_{jit}$. However, they confirm in ideal environment condition and without a jitter the sampled output or random is deterministic under a period of $T{Q}= \ {K_{D}T_{CLK}} \ = \ {K_{m}T_{CLG}}$. Then, they conclude in a real condition $\sigma_{jit} \ \neq \ 0 $ the randomness is not deterministic and depending on jitter distribution where the $MAX(\Delta T_{min})= \ T_{CLK}*GCD(2K_{M},K_{D})/4K_{M}$.
9 Where, in \cite{vsimka2005embedded} the authors demonstrate by taking \cite{fischer2003true} as model and combined more than one PLL in parallel or series to increase the significantly sensitivity on the jitter $S= \ F_{CLK}MAX(\Delta T_{min})$ and the output-bit of the generator compared to the use of one PLL. The configuration of multiple PLL are based on input/output length, VCO frequency and MUL/DIV factors ($K_{M}/K_{D}$). In \cite{simka2011testing} the authors test the impact of the the change on operation condition environment as temperature of an PLL and illustrate that with low bandwidth of PFF cause a higher number of the critical samples, decreases the output jitter and thus increase the tracking jitter. As an PLL application system, the work proposed in \cite{varchola2008hardware} they explore an embedded system with TRNG and based on PLL to extract randomness from the jitter and propose two version where the slower of 40kbps can pass the statistic tests.
12 \textit{ring oxialltor}
13 In \cite{kohlbrenner2004embedded} and in \cite{klein2009design}, the authors propose a TRNG based on two ring oscillators clocked by different clock generated by an internal PLL on FPGA. The authors also extract the jitter of the 2 RO implement in only one CLB slice using a simpler. Where, in \cite{dichtl2007high}, propose a new approach that can replace RO based on inverters using XOR combination between Fibonacci (FIRO) and Galois ring oscillators (GARO). the main key consists of a number of inverters and connected in a cascade together with XOR logic gates forming a feedback in an analogous way where the feedback polynomial form is $f(x) = \ (1+x)h(x)$ where $h(1)=1$ and the result show with the new method can achieve a stable state less than classical RO.
15 In \cite{tsoi2003compact}, the authors propose a Hybrid implementation on FPGA of TRNG based on RO and PRNG based on BBS generators and with high operation frequency of 400Mhz. However, they generate a low off-chip frequency based on resistor and capacitors RC and it was notice by implementing BBS using ALU structure for squaring and modulo operation the period will be [$(4.5*n^{2} \ + n)$].
18 \textit{Self-timed ring STR}
19 In \cite{cherkaoui2013self} and \cite{cherkaoui2012comparison}, the authors propose another alternative more based on Self-Timed Ring (STR) robust to environment (power, temperature) than RO based inverter. The SRT approach consist of a ripple of L stage of FIFO as a ring $(C_{i})_{1}{_{\leq}}{_{i}}{_{\leq}}{_{L}}$ with a phase of $\Delta \varphi = T/2L$, and extract jitter of each oscillator stage using two asynchronous handshaking protocol as even that can be "taken" or "bubble". However, the outputs randomness bits event $(S_{i})_{1}{_{\leq}}{_{i}}{_{\leq}}{_{L}}$ will be samples using a flip-flop by the main clock and the result will be combined with a XOR operation $\psi = \ s_{1} \ \oplus \ s_{2} \ \oplus \ ... \ \oplus \ s_{L}$. Secondly, the authors suggest that to avoid the limitation frequency of the STR by the long period delay, the maximum frequency is achieve when the propagation delay (forward and reverse static delay) is near to ring accuracy (N° of token and bubble) and [$N_{T}/N_{B} \ \cong \ D_{ff}/_D{rr} \ \simeq \ 1$].
22 \textit{Metastability}
23 In \cite{vasyltsov2008fast}, the authors present a study of using \emph{Metastability} phenomena as a entropy source generated by 5 IRO stage. They claim that by implementing the inverter as loop ring and using a Control Clock Generator to switch the connectivity between the IRO stages flowing two mode (MS, Generation), the output voltage converges to metastability level and stays longer than using bi-stable circuit (Flip-Flop) causing a high entropy. However, the authors wan to estimate the robustness of the system after applying the sampling process in a different process and environment variation modes using CMOS process and FPGA, and they find that it must added another stage for a higher quality output as decreasing the operation rate, applying a Von-Neumann post-processing and influences the loads (RC parasitic) of the last inverter, when it was noted that just post-processing is used in FPGA.
25 Another metastability uses as a RNG founded in \cite{majzoobi2011fpga}, where the authors propose a TRNG using the metastability of the flip-flop when there is a violation in setup/hold time. The system is based on closed-loop feedback mechanism for auto-adjustment on delay $\Delta$ controlled by the Programmable delay lines (PDLs) stage based on LUT to avoid violation and maintain the metastability. However, the system use at-speed monitor to keep tracking the output bit probability and proportional-integral (PI) controller to decides to add/subtract the delay difference ($\Delta \rightarrow 0$). The probability of the output is $Prob{Out = 1} = Q(\Delta/sigma)$ where $Q(x)= {1/\surd{4\Pi}}{\int{_{x}{^{\infty}}} expr{(-u^{2}/2)du}}$. Where, the updated/corrected delay difference is the difference between the bias/skew caused by the routing asymmetric with the delay induce by the environment condition and the correct delay injected by the PDL ($\Delta=\Delta_{p}+\Delta_{b}-\Delta_{f}$). A revision version proposed by \cite{lee2014metastability}, to analyze the probability and maintain metastability state for a long period to avoid the deterministic state. however they use an extract hardware resource as memory for storing the outputs and use Hamming weight to calculate the probability bits histories.
