lib/implementations/demux_impl.xml

   1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
   2 <block_impl ref_name="demux.xml" ref_md5="">
   3   <comments>
   4     <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
   5     <date creation="2015-04-27" />
   6     <related_files list=""/>
   7     <description>
   8       This component is a synchronous demultiplixer with variable number of outputs
   9     </description>
  10     <notes>
  11       No notes
  12     </notes>
  13   </comments>
  14
  15   <libraries>
  16     <library name="IEEE">
  17       <package name="std_logic_1164" use="all"/>
  18       <package name="numeric_std" use="all"/>
  19     </library>
  20   </libraries>
  21
  22   <architecture>
  23
  24     signal sel_s      : unsigned(@eval{@val{sel_width}-1} downto 0);
  25     signal val_i_dly  : std_logic_vector(@eval{@val{val_width}-1} downto 0};
  26
  27     @foreach{val_o}
  28     signal @{val_o}_enb : std_logic;
  29     @endforeach
  30
  31     begin
  32
  33     sel_s &lt;= @{sel_i};
  34
  35     delay_input : process(@{clk}, @{rst})
  36     begin
  37     if(@{rst}='1') then
  38       val_i_dly &lt;= (others => '0');
  39     elsif(rising_edge(@{clk})) then
  40       val_i_dly &lt;= @{val_i};
  41     end if;
  42     end process delay_input;
  43
  44
  45     demux : process(@{clk}, @{rst})
  46     begin
  47     if(@{rst}='1') then
  48
  49       @foreach{val_o}
  50       @{val_o}_enb &lt;= '0';
  51       @endforeach
  52
  53       elsif(rising_edge(@{clk})) then
  54
  55       @foreach{val_o}
  56       @{val_o}_enb &lt;= '0';
  57       @endforeach
  58
  59       @caseeach{val_o,sel_s,@#:1}
  60       @{val_o}_enb &lt;= '1';
  61       @endcaseeach
  62
  63       end if;
  64     end process demux;
  65
  66     @foreach{val_o}
  67     @{val_o}   &lt;= val_i_dly when (@{val_o}_enb = '1') else (others => '0');
  68     @endforeach
  69
  70   </architecture>
  71 </block_impl>