finished VHDL gen

diff --git a/DelayInputModifier.cpp b/DelayInputModifier.cpp
index a60d7e27a23440da0f40c862a33e892317eda7b9..db89107a4614a9a9bad39bde1cac761a8c562329 100644 (file)
--- a/DelayInputModifier.cpp
+++ b/DelayInputModifier.cpp
@@ -29,10 +29,10 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
   ConnectedInterface* toIface = AI_TO_CON(toCtlIface->getAssociatedIface());\r
   QString toName = toIface->getOwner()->getName()+"_"+toIface->getName();\r
   QString toCtlName = toCtlIface->getOwner()->getName()+"_"+toCtlIface->getName();\r
-  QString dm1 = "";\r
   QString dm2 = "";\r
-  dm1.setNum(delayLength-1);\r
+  QString dm3 = "";\r
   dm2.setNum(delayLength-2);\r
+  dm3.setNum(delayLength-3);\r
   QString ret="";\r
   QString clkName = "clk";\r
   QString resetName = "reset";\r
@@ -50,12 +50,12 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "      "+toName+"_mod     <= (others => '0');\n";\r
     ret += "      "+toCtlName+"_mod  <= '0';\n";\r
     ret += "    elsif rising_edge("+clkName+") then\n";\r
-    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm1+");\n";\r
-    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm1+");\n";\r
+    ret += "      "+toName+"_mod <= "+toName+"_dly("+dm2+");\n";\r
+    ret += "      "+toCtlName+"_mod  <= "+toCtlName+"_dly("+dm2+");\n";\r
     ret += "      "+toName+"_dly(0)  <= "+fromIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
     ret += "      "+toCtlName+"_dly(0)  <= "+fromCtlIface->toVHDL(AbstractInterface::Instance,0)+";\n";\r
-    ret += "      "+toName+"_dly(1 to "+dm1+")  <= "+toName+"_dly(0 to "+dm2+");\n";\r
-    ret += "      "+toCtlName+"_dly(1 to "+dm1+")  <= "+toCtlName+"_dly(0 to "+dm2+");\n";\r
+    ret += "      "+toName+"_dly(1 to "+dm2+")  <= "+toName+"_dly(0 to "+dm3+");\n";\r
+    ret += "      "+toCtlName+"_dly(1 to "+dm2+")  <= "+toCtlName+"_dly(0 to "+dm3+");\n";\r
     ret += "    end if;\n";\r
     ret += "  end process "+toName + "_mod_process;\n";\r
   }\r
@@ -68,8 +68,8 @@ QString DelayInputModifier::toVHDL(int context, int flags) throw(Exception) {
     ret += "  signal "+sig+"\n";\r
     QString wStr="";\r
     wStr.setNum(toIface->getWidth());\r
-    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm1+");\n";\r
-    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm1+");\n";\r
+    ret += "  signal "+toName+"_dly :  vector_of_std_logic_vector"+wStr+"(0 to "+dm2+");\n";\r
+    ret += "  signal "+toCtlName+"_dly :  vector_of_std_logic(0 to "+dm2+");\n";\r
   }\r
 \r
   return ret;\r

diff --git a/Dispatcher.cpp b/Dispatcher.cpp
index b9e09a946151f447a71b6eb287cffa586f6fe39b..cdf8ee3b1c281ba5381bb56b605440f2de7a698e 100644 (file)
--- a/Dispatcher.cpp
+++ b/Dispatcher.cpp
@@ -256,11 +256,18 @@ void Dispatcher::generateVHDL() throw(Exception) {
   }
   out << endl;
   out << "VL_SRC := ${XILINX}/verilog/src/glbl.v" << endl << endl;
-  out << "TB_SRC := $(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
+  out << "TB_SRC := $(TB_DIR)/read_csv.vhd \\" << endl;
+  out << "\t$(TB_DIR)/$(PROJECT_NAME)_tb.vhd" << endl << endl;
   out << "SIMU_EXE := $(PROJECT_NAME)_tb" << endl << endl;
 
   paramFile.close();
 
+  QString msg = "VHDL generation completed successfully. Go to ";
+  msg += params->projectPath+" and type the following commands to launch a simulation:\n";
+  msg += "\tmake clean\n";
+  msg += "\tmake\n";
+  msg += "\tmake view\n";
+  QMessageBox::information(mainWindow,"VHDL generation", msg, QMessageBox::Ok);
 
 }
 

diff --git a/GroupBlock.cpp b/GroupBlock.cpp
index 5b4f34e2c9e2090c90f5d8e91ef042c7513ab1b9..ab76563048265cd375aabeaeecff9a6d0f606f7b 100644 (file)
--- a/GroupBlock.cpp
+++ b/GroupBlock.cpp
@@ -491,7 +491,18 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
   out << "  --  SIGNALS" << endl;
   out << "  ----------------------------" << endl << endl;
 
-// "normal" signals
+  // signals to synchronize inputs
+  out << "  -- signals to synchronize inputs" << endl;
+  foreach(AbstractInterface* iface, getInputs()) {
+    if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+      QString name = iface->toVHDL(AbstractInterface::Signal,0);
+      name.replace(" : ","_sync : ");
+      out << "  signal " << name<< endl;
+    }
+  }
+  out << endl;
+
+  // "normal" signals
   foreach(AbstractBlock* block, blocks) {
     try {
       out << "  -- signals from output ports of " << block->getName() << endl;
@@ -610,7 +621,12 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
           }
         }
         else if (fromIface->isGroupInterface()) {
-          portMap += "      " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+          if ((fromIface->getOwner()->isTopGroupBlock()) && ((fromIface->getPurpose() == AbstractInterface::Data)||(fromIface->getPurpose() == AbstractInterface::Control))) {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getOwner()->getName()+ "_"+ fromIface->getName() + "_sync,\n";
+          }
+          else {
+            portMap += "      " + connIface->getName() + " => " + fromIface->getName() + ",\n";
+          }
         }
       }
       if (listOutputs.size()>0) {
@@ -658,6 +674,39 @@ void GroupBlock::generateArchitecture(QTextStream& out, QDomElement &elt) throw(
     }
   }
 
+  if (topGroup) {
+    // generate input sync process
+    out << "  -- process to synchronize inputs of top group" << endl;
+    out << "sync_inputs : process(from_clkrstgen_clk,from_clkrstgen_reset)" << endl;
+    out << "  begin" << endl;
+    out << "    if from_clkrstgen_reset = '1' then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= '0';" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= (others => '0');" << endl;
+        }
+      }
+    }
+    out << "    elsif rising_edge(from_clkrstgen_clk) then" << endl;
+    foreach(AbstractInterface* iface, getInputs()) {
+      if ((iface->getPurpose() == AbstractInterface::Data)||(iface->getPurpose() == AbstractInterface::Control)) {
+        if (iface->getWidth() == 0) {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+        else {
+          out << "      " << name << "_" << iface->getName() << "_sync <= " << iface->getName() << ";" << endl;
+        }
+      }
+    }
+    out << "    end if;" << endl;
+    out << "  end process sync_inputs;" << endl;
+
+    out << endl;
+  }
+
   out << "end architecture rtl;" << endl;
 }
 

diff --git a/blast.creator.user b/blast.creator.user
index 3230c1f88437c718d44a06531ac083cf1c1fd311..8cb263a824af06232bd01dd1a8fcff7c4c0b8835 100644 (file)
--- a/blast.creator.user
+++ b/blast.creator.user
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE QtCreatorProject>
-<!-- Written by QtCreator 4.2.0, 2018-03-30T16:40:46. -->
+<!-- Written by QtCreator 4.2.0, 2018-04-04T13:40:10. -->
 <qtcreator>
  <data>
   <variable>EnvironmentId</variable>

diff --git a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
index e9415791a2448b527085f8b89fe09401f9a352d2..055ec26f337e042fd294bb38ef4a4386201d2692 100644 (file)
--- a/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
+++ b/lib/implementations/rgb3sx8_to_ycbcr_3DSP_impl.xml
@@ -33,7 +33,6 @@ signal do_sum_cr : std_logic;
 signal do_sum_cr_dly : std_logic;
 signal do_sum_cb : std_logic;
 signal do_sum_cb_dly : std_logic;
-signal do_out : std_logic;
 signal do_out_cr : std_logic;
 signal do_out_cb : std_logic;
 signal do_out_y : std_logic;
@@ -69,8 +68,6 @@ signal a_cb : std_logic_vector(17 downto 0);
 signal b_cb : std_logic_vector(17 downto 0);
 signal s_cb : std_logic_vector(47 downto 0);
 
-signal compo_out : std_logic_vector(7 downto 0);
-
 begin
 
 y_multiplier : mult_accum
@@ -156,7 +153,8 @@ end process multy_process;
 sumy_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_y <= '0';
+bypass_y <= '1';
+do_sum_y_dly <= '0';
 y <= to_signed(0, 9);
 y_dly1 <= to_signed(0, 9);
 y_dly2 <= to_signed(0, 9);
@@ -215,7 +213,8 @@ end process multcb_process;
 sumcb_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cb <= '0';
+bypass_cb <= '1';
+do_sum_cb_dly <= '0';
 cb <= to_signed(0, 9);
 cb_dly1 <= to_signed(0, 9);
 elsif rising_edge(@{clk}) then
@@ -271,7 +270,8 @@ end process multcr_process;
 sumcr_process : process (@{clk}, @{reset})
 begin
 if @{reset} = '1' then
-bypass_cr <= '0';
+bypass_cr <= '1';
+do_sum_cr_dly <= '0';
 cr <= to_signed(0, 9);
 do_out_cr <= '0';