--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<block_impl ref_name="generator-cst.xml" ref_md5="">
+ <comments>
+ <author firstname="stephane" lastname="Domas" mail="sdomas@univ-fcomte.fr" />
+ <date creation="2015-05-10" />
+ <related_files list=""/>
+ <description>
+ This component is a generator of a sequence of V fixed values, followed by Z idle cycles.
+ </description>
+ <notes>
+ No notes
+ </notes>
+ </comments>
+
+ <libraries>
+ <library name="IEEE">
+ <package name="std_logic_1164" use="all"/>
+ <package name="numeric_std" use="all"/>
+ </library>
+ </libraries>
+
+ <architecture>
+
+ </architecture>
+
+ <patterns>
+ <delta value="$seq_length+$idle_length" />
+ <consumption>
+ </consumption>
+ <production counter="">
+ <output name="data_o" pattern="1{$seq_length}X{$idle_length}" />
+ </production>
+ </patterns>
+</block_impl>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<block>
+ <informations>
+ <name>
+ generator-cst
+ </name>
+ <category ids="6" />
+ <description>
+ <brief>
+ generates V consecutives constant values, followed by Z idle cycles
+ </brief>
+ <detailed>
+ generates V consecutives constant values, followed by Z idle cycles
+ </detailed>
+ </description>
+ </informations>
+
+ <parameters>
+ <parameter name="data_width" type="positive" value="8" context="user"/>
+ <parameter name="seq_length" type="positive" value="10" context="user"/>
+ <parameter name="idle_length" type="positive" value="5" context="user"/>
+ </parameters>
+
+ <interfaces>
+ <inputs>
+ <input name="clk" width="1" purpose="clock" />
+ <input name="rst" width="1" purpose="reset" />
+ </inputs>
+ <outputs>
+ <output name="data_o" width="$data_width"/>
+ <control iface="data_o"/>
+ </outputs>
+ </interfaces>
+
+</block>