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finished VHDL gen. (but have to test further
[blast.git] / lib /
2018-03-30 stephane Domasfinished VHDL gen. (but have to test further
2018-03-29 stephane Domasstarted VHDL generation of GroupBlock
2018-03-23 stephane Domaswipe some useluess files
2018-03-23 domas stephanestarted top group gen, added project subdirs
2018-03-22 sdomasadded sources managment
2018-03-05 sdomasmoved generate vhdl methods
2018-03-05 stephane Domasafter merge
2018-03-05 stephane Domasadded new project dialog
2018-01-24 stephane Domasdebugged clk/rst auto conn
2018-01-24 stephane Domascorrect bug with clkrstgen
2018-01-24 stephane Domasadd clk/rst to groups
2018-01-14 stephane Domasadd graph modif, progress on vhdl generation
2018-01-10 stephane Domasmodif in VHDLConverter
2017-12-08 stephane Domaschanges in output pattern comput
2017-05-22 stephane Domaspatter compat continued
2017-05-19 stephane Domasadded admittance computation
2017-05-18 stephane Domasmodified pattern to use only QMap
2017-05-14 stephane Domaspattern comput done
2017-05-12 stephane Domasadded generator-cst
2017-05-12 stephane Domasstarted adding delta comput
2017-05-10 stephane Domascorrect relative positionning of source/group
2017-05-09 stephane Domasadded source items
2017-05-08 stephane Domasstart modifying read/write blocks and project to take...
2017-05-05 stephane Domasadded creation of control ifaces
2017-05-04 stephane Domasadding show/hide wb ifaces
2017-05-04 stephane Domasbegun integration of control ifaces
2017-05-03 Stéphane Domasadding xsd files to master
2017-05-03 Stéphane Domasadding xsd files to master
2017-05-03 Stéphane Domasadded impl xsd + patterns in impls
2017-05-03 Stéphane Domasremoved leve attr. from interfaces
2017-04-26 Stéphane Domas1st commit of all files