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AND Private Git Repository - blast.git/log
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stephane Domas [Wed, 2 May 2018 20:20:39 +0000 (22:20 +0200)]
changed ref/impls xsd and xml
stephane Domas [Wed, 2 May 2018 14:34:45 +0000 (16:34 +0200)]
finished conn mode of library
stephane Domas [Mon, 30 Apr 2018 16:24:27 +0000 (18:24 +0200)]
added clk/rst link when creating a block
stephane Domas [Fri, 27 Apr 2018 14:44:07 +0000 (16:44 +0200)]
adding link between ifaces and clk
stephane Domas [Fri, 20 Apr 2018 14:47:52 +0000 (16:47 +0200)]
added context to dispatcher op.
stephane Domas [Fri, 13 Apr 2018 14:52:06 +0000 (16:52 +0200)]
start to include clkdomain converters
stephane Domas [Fri, 6 Apr 2018 11:34:03 +0000 (13:34 +0200)]
finished VHDL gen
stephane Domas [Fri, 30 Mar 2018 14:41:33 +0000 (16:41 +0200)]
finished VHDL gen. (but have to test further
stephane Domas [Thu, 29 Mar 2018 20:16:28 +0000 (22:16 +0200)]
nearly finished GroupBlock VHDL gen
stephane Domas [Thu, 29 Mar 2018 15:20:07 +0000 (17:20 +0200)]
started VHDL generation of GroupBlock
stephane Domas [Fri, 23 Mar 2018 16:45:35 +0000 (17:45 +0100)]
wipe some useluess files
domas stephane [Fri, 23 Mar 2018 15:06:56 +0000 (16:06 +0100)]
started top group gen, added project subdirs
domas stephane [Fri, 23 Mar 2018 15:06:38 +0000 (16:06 +0100)]
started top group gen, added project subdirs
sdomas [Thu, 22 Mar 2018 10:05:50 +0000 (11:05 +0100)]
added sources managment
stephane Domas [Thu, 22 Mar 2018 07:51:47 +0000 (08:51 +0100)]
moved vhdl gen. into block
sdomas [Mon, 5 Mar 2018 11:13:49 +0000 (12:13 +0100)]
moved generate vhdl methods
stephane Domas [Mon, 5 Mar 2018 10:00:46 +0000 (11:00 +0100)]
after merge
stephane Domas [Mon, 5 Mar 2018 09:54:36 +0000 (10:54 +0100)]
added new project dialog
stephane Domas [Wed, 24 Jan 2018 20:11:31 +0000 (21:11 +0100)]
debugged clk/rst auto conn
stephane Domas [Wed, 24 Jan 2018 17:18:27 +0000 (18:18 +0100)]
correct bug with clkrstgen
stephane Domas [Wed, 24 Jan 2018 12:27:01 +0000 (13:27 +0100)]
add clk/rst to groups
stephane Domas [Sun, 14 Jan 2018 23:02:16 +0000 (00:02 +0100)]
add graph modif, progress on vhdl generation
stephane Domas [Wed, 10 Jan 2018 09:52:39 +0000 (10:52 +0100)]
modif in VHDLConverter
stephane Domas [Fri, 8 Dec 2017 16:50:39 +0000 (17:50 +0100)]
changes in output pattern comput
stephane Domas [Sun, 15 Oct 2017 18:16:05 +0000 (20:16 +0200)]
changed VHDL converter
stephane Domas [Fri, 13 Oct 2017 14:26:10 +0000 (16:26 +0200)]
changed name of the class that converts VHDL -> XML
stephane Domas [Tue, 23 May 2017 15:27:17 +0000 (17:27 +0200)]
corrected some warnings
domas stephane [Mon, 22 May 2017 17:37:09 +0000 (19:37 +0200)]
modifying pattern methods to throw exceptions
domas stephane [Mon, 22 May 2017 09:05:22 +0000 (11:05 +0200)]
finished compat. computation
stephane Domas [Mon, 22 May 2017 07:28:30 +0000 (09:28 +0200)]
patter compat continued
stephane Domas [Fri, 19 May 2017 14:41:28 +0000 (16:41 +0200)]
added admittance computation
stephane Domas [Thu, 18 May 2017 15:01:11 +0000 (17:01 +0200)]
modified pattern to use only QMap
stephane Domas [Sun, 14 May 2017 19:45:38 +0000 (21:45 +0200)]
pattern comput done
stephane Domas [Fri, 12 May 2017 14:48:06 +0000 (16:48 +0200)]
added generator-cst
stephane Domas [Fri, 12 May 2017 14:46:45 +0000 (16:46 +0200)]
started adding delta comput
stephane Domas [Thu, 11 May 2017 19:37:28 +0000 (21:37 +0200)]
started to include patterns in implementation
stephane Domas [Thu, 11 May 2017 15:55:06 +0000 (17:55 +0200)]
added patterns and started OP computation
stephane Domas [Wed, 10 May 2017 20:30:19 +0000 (22:30 +0200)]
changed connection process
stephane Domas [Wed, 10 May 2017 14:31:11 +0000 (16:31 +0200)]
correct relative positionning of source/group
stephane Domas [Tue, 9 May 2017 20:33:37 +0000 (22:33 +0200)]
source connection ok
stephane Domas [Tue, 9 May 2017 17:56:09 +0000 (19:56 +0200)]
added an example of source block
stephane Domas [Tue, 9 May 2017 17:55:28 +0000 (19:55 +0200)]
added source items
stephane Domas [Mon, 8 May 2017 18:46:44 +0000 (20:46 +0200)]
start modifying read/write blocks and project to take into account control ifaces
stephane Domas [Fri, 5 May 2017 12:30:12 +0000 (14:30 +0200)]
added creation of control ifaces
stephane Domas [Thu, 4 May 2017 19:31:01 +0000 (21:31 +0200)]
adding show/hide wb ifaces
stephane Domas [Thu, 4 May 2017 15:29:33 +0000 (17:29 +0200)]
begun integration of control ifaces
Stéphane Domas [Wed, 3 May 2017 15:56:29 +0000 (17:56 +0200)]
adding blast in gitignore
Stéphane Domas [Wed, 3 May 2017 15:55:28 +0000 (17:55 +0200)]
adding xsd files to master
Stéphane Domas [Wed, 3 May 2017 15:55:05 +0000 (17:55 +0200)]
adding xsd files to master
Stéphane Domas [Wed, 3 May 2017 15:52:22 +0000 (17:52 +0200)]
added impl xsd + patterns in impls
sdomas [Wed, 3 May 2017 09:19:27 +0000 (11:19 +0200)]
removed level attribute from interface
Stéphane Domas [Wed, 3 May 2017 09:18:41 +0000 (11:18 +0200)]
removed leve attr. from interfaces
stephane Domas [Wed, 3 May 2017 06:26:43 +0000 (08:26 +0200)]
loading project corrected
stephane Domas [Thu, 27 Apr 2017 21:27:55 +0000 (23:27 +0200)]
removing save from repo
stephane Domas [Thu, 27 Apr 2017 21:27:03 +0000 (23:27 +0200)]
adding save to gitignore
stephane Domas [Thu, 27 Apr 2017 21:25:12 +0000 (23:25 +0200)]
insert/move/remove block/groups/interface done. Next to fo: loading project file
Stéphane Domas [Wed, 26 Apr 2017 16:52:17 +0000 (18:52 +0200)]
correcting bugs but still exsitings
Stéphane Domas [Wed, 26 Apr 2017 12:22:54 +0000 (14:22 +0200)]
1st commit of all files
Stéphane Domas [Wed, 26 Apr 2017 12:22:04 +0000 (14:22 +0200)]
1st commit of all files
Stéphane Domas [Wed, 26 Apr 2017 12:19:43 +0000 (14:19 +0200)]
1st commit of all files
Stéphane Domas [Wed, 26 Apr 2017 12:17:46 +0000 (14:17 +0200)]
1st commit of all files
Stéphane Domas [Wed, 26 Apr 2017 11:57:01 +0000 (13:57 +0200)]
1st commit in order to initialiaze the remote repository
